185135283SDan Handley/* 21c3ea103SAntonio Nino Diaz * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 385135283SDan Handley * 485135283SDan Handley * Redistribution and use in source and binary forms, with or without 585135283SDan Handley * modification, are permitted provided that the following conditions are met: 685135283SDan Handley * 785135283SDan Handley * Redistributions of source code must retain the above copyright notice, this 885135283SDan Handley * list of conditions and the following disclaimer. 985135283SDan Handley * 1085135283SDan Handley * Redistributions in binary form must reproduce the above copyright notice, 1185135283SDan Handley * this list of conditions and the following disclaimer in the documentation 1285135283SDan Handley * and/or other materials provided with the distribution. 1385135283SDan Handley * 1485135283SDan Handley * Neither the name of ARM nor the names of its contributors may be used 1585135283SDan Handley * to endorse or promote products derived from this software without specific 1685135283SDan Handley * prior written permission. 1785135283SDan Handley * 1885135283SDan Handley * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1985135283SDan Handley * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2085135283SDan Handley * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2185135283SDan Handley * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2285135283SDan Handley * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2385135283SDan Handley * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2485135283SDan Handley * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2585135283SDan Handley * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2685135283SDan Handley * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2785135283SDan Handley * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2885135283SDan Handley * POSSIBILITY OF SUCH DAMAGE. 2985135283SDan Handley */ 3085135283SDan Handley 3185135283SDan Handley#include <arch.h> 3285135283SDan Handley#include <asm_macros.S> 3385135283SDan Handley#include <bl_common.h> 3423d39dbcSSandrine Bailleux#include <cortex_a53.h> 3585135283SDan Handley#include <cortex_a57.h> 361dbe3159SSandrine Bailleux#include <cortex_a72.h> 3785135283SDan Handley#include <v2m_def.h> 3885135283SDan Handley#include "../juno_def.h" 3985135283SDan Handley 4085135283SDan Handley 4185135283SDan Handley .globl plat_reset_handler 42371d4399SDavid Wang .globl plat_arm_calc_core_pos 4385135283SDan Handley 4423d39dbcSSandrine Bailleux#define JUNO_REVISION(rev) REV_JUNO_R##rev 4523d39dbcSSandrine Bailleux#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev 4623d39dbcSSandrine Bailleux#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ 4723d39dbcSSandrine Bailleux jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) 4823d39dbcSSandrine Bailleux 4985135283SDan Handley /* -------------------------------------------------------------------- 5023d39dbcSSandrine Bailleux * Helper macro to jump to the given handler if the board revision 5123d39dbcSSandrine Bailleux * matches. 5223d39dbcSSandrine Bailleux * Expects the Juno board revision in x0. 5323d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 5423d39dbcSSandrine Bailleux */ 5523d39dbcSSandrine Bailleux .macro jump_to_handler _revision, _handler 5623d39dbcSSandrine Bailleux cmp x0, #\_revision 5723d39dbcSSandrine Bailleux b.eq \_handler 5823d39dbcSSandrine Bailleux .endm 5923d39dbcSSandrine Bailleux 6023d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 6123d39dbcSSandrine Bailleux * Helper macro that reads the part number of the current CPU and jumps 6223d39dbcSSandrine Bailleux * to the given label if it matches the CPU MIDR provided. 6385135283SDan Handley * 6423d39dbcSSandrine Bailleux * Clobbers x0. 6523d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 6623d39dbcSSandrine Bailleux */ 6723d39dbcSSandrine Bailleux .macro jump_if_cpu_midr _cpu_midr, _label 6823d39dbcSSandrine Bailleux mrs x0, midr_el1 6923d39dbcSSandrine Bailleux ubfx x0, x0, MIDR_PN_SHIFT, #12 7023d39dbcSSandrine Bailleux cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 7123d39dbcSSandrine Bailleux b.eq \_label 7223d39dbcSSandrine Bailleux .endm 7323d39dbcSSandrine Bailleux 7423d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 7523d39dbcSSandrine Bailleux * Platform reset handler for Juno R0. 7623d39dbcSSandrine Bailleux * 7723d39dbcSSandrine Bailleux * Juno R0 has the following topology: 7823d39dbcSSandrine Bailleux * - Quad core Cortex-A53 processor cluster; 7923d39dbcSSandrine Bailleux * - Dual core Cortex-A57 processor cluster. 8023d39dbcSSandrine Bailleux * 8123d39dbcSSandrine Bailleux * This handler does the following: 8285135283SDan Handley * - Implement workaround for defect id 831273 by enabling an event 8385135283SDan Handley * stream every 65536 cycles. 8485135283SDan Handley * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 8585135283SDan Handley * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 8623d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 8723d39dbcSSandrine Bailleux */ 8823d39dbcSSandrine Bailleuxfunc JUNO_HANDLER(0) 8923d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 9023d39dbcSSandrine Bailleux * Enable the event stream every 65536 cycles 9123d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 9223d39dbcSSandrine Bailleux */ 9323d39dbcSSandrine Bailleux mov x0, #(0xf << EVNTI_SHIFT) 9423d39dbcSSandrine Bailleux orr x0, x0, #EVNTEN_BIT 9523d39dbcSSandrine Bailleux msr CNTKCTL_EL1, x0 9623d39dbcSSandrine Bailleux 9723d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 9823d39dbcSSandrine Bailleux * Nothing else to do on Cortex-A53. 9923d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 10023d39dbcSSandrine Bailleux */ 10123d39dbcSSandrine Bailleux jump_if_cpu_midr CORTEX_A53_MIDR, 1f 10223d39dbcSSandrine Bailleux 10323d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 10423d39dbcSSandrine Bailleux * Cortex-A57 specific settings 10523d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 10623d39dbcSSandrine Bailleux */ 10723d39dbcSSandrine Bailleux mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 10823d39dbcSSandrine Bailleux (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) 10923d39dbcSSandrine Bailleux msr L2CTLR_EL1, x0 11023d39dbcSSandrine Bailleux1: 11123d39dbcSSandrine Bailleux isb 11223d39dbcSSandrine Bailleux ret 11323d39dbcSSandrine Bailleuxendfunc JUNO_HANDLER(0) 11423d39dbcSSandrine Bailleux 11523d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 11623d39dbcSSandrine Bailleux * Platform reset handler for Juno R1. 11785135283SDan Handley * 11823d39dbcSSandrine Bailleux * Juno R1 has the following topology: 11923d39dbcSSandrine Bailleux * - Quad core Cortex-A53 processor cluster; 12023d39dbcSSandrine Bailleux * - Dual core Cortex-A57 processor cluster. 12123d39dbcSSandrine Bailleux * 12223d39dbcSSandrine Bailleux * This handler does the following: 12385135283SDan Handley * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 12423d39dbcSSandrine Bailleux * 12585135283SDan Handley * Note that: 12685135283SDan Handley * - The default value for the L2 Tag RAM latency for Cortex-A57 is 12785135283SDan Handley * suitable. 12823d39dbcSSandrine Bailleux * - Defect #831273 doesn't affect Juno R1. 12985135283SDan Handley * -------------------------------------------------------------------- 13085135283SDan Handley */ 13123d39dbcSSandrine Bailleuxfunc JUNO_HANDLER(1) 13285135283SDan Handley /* -------------------------------------------------------------------- 13323d39dbcSSandrine Bailleux * Nothing to do on Cortex-A53. 13485135283SDan Handley * -------------------------------------------------------------------- 13585135283SDan Handley */ 13623d39dbcSSandrine Bailleux jump_if_cpu_midr CORTEX_A57_MIDR, A57 13785135283SDan Handley ret 13885135283SDan Handley 13985135283SDan HandleyA57: 14085135283SDan Handley /* -------------------------------------------------------------------- 14185135283SDan Handley * Cortex-A57 specific settings 14285135283SDan Handley * -------------------------------------------------------------------- 14385135283SDan Handley */ 14423d39dbcSSandrine Bailleux mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) 14585135283SDan Handley msr L2CTLR_EL1, x0 14685135283SDan Handley isb 14785135283SDan Handley ret 14823d39dbcSSandrine Bailleuxendfunc JUNO_HANDLER(1) 14923d39dbcSSandrine Bailleux 15023d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 15123d39dbcSSandrine Bailleux * Platform reset handler for Juno R2. 15223d39dbcSSandrine Bailleux * 15323d39dbcSSandrine Bailleux * Juno R2 has the following topology: 15423d39dbcSSandrine Bailleux * - Quad core Cortex-A53 processor cluster; 15523d39dbcSSandrine Bailleux * - Dual core Cortex-A72 processor cluster. 15623d39dbcSSandrine Bailleux * 1571dbe3159SSandrine Bailleux * This handler does the following: 1581dbe3159SSandrine Bailleux * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 1591dbe3159SSandrine Bailleux * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 1601dbe3159SSandrine Bailleux * 1611dbe3159SSandrine Bailleux * Note that: 1621dbe3159SSandrine Bailleux * - Defect #831273 doesn't affect Juno R2. 16323d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 16423d39dbcSSandrine Bailleux */ 16523d39dbcSSandrine Bailleuxfunc JUNO_HANDLER(2) 1661dbe3159SSandrine Bailleux /* -------------------------------------------------------------------- 1671dbe3159SSandrine Bailleux * Nothing to do on Cortex-A53. 1681dbe3159SSandrine Bailleux * -------------------------------------------------------------------- 1691dbe3159SSandrine Bailleux */ 1701dbe3159SSandrine Bailleux jump_if_cpu_midr CORTEX_A72_MIDR, A72 1711dbe3159SSandrine Bailleux ret 1721dbe3159SSandrine Bailleux 1731dbe3159SSandrine BailleuxA72: 1741dbe3159SSandrine Bailleux /* -------------------------------------------------------------------- 1751dbe3159SSandrine Bailleux * Cortex-A72 specific settings 1761dbe3159SSandrine Bailleux * -------------------------------------------------------------------- 1771dbe3159SSandrine Bailleux */ 1781dbe3159SSandrine Bailleux mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 1791dbe3159SSandrine Bailleux (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) 1801dbe3159SSandrine Bailleux msr L2CTLR_EL1, x0 1811dbe3159SSandrine Bailleux isb 18223d39dbcSSandrine Bailleux ret 18323d39dbcSSandrine Bailleuxendfunc JUNO_HANDLER(2) 18423d39dbcSSandrine Bailleux 18523d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 18623d39dbcSSandrine Bailleux * void plat_reset_handler(void); 18723d39dbcSSandrine Bailleux * 18823d39dbcSSandrine Bailleux * Determine the Juno board revision and call the appropriate reset 18923d39dbcSSandrine Bailleux * handler. 19023d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 19123d39dbcSSandrine Bailleux */ 19223d39dbcSSandrine Bailleuxfunc plat_reset_handler 19323d39dbcSSandrine Bailleux /* Read the V2M SYS_ID register */ 19423d39dbcSSandrine Bailleux mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) 19523d39dbcSSandrine Bailleux ldr w1, [x0] 19623d39dbcSSandrine Bailleux /* Extract board revision from the SYS_ID */ 19723d39dbcSSandrine Bailleux ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4 19823d39dbcSSandrine Bailleux 19923d39dbcSSandrine Bailleux JUMP_TO_HANDLER_IF_JUNO_R(0) 20023d39dbcSSandrine Bailleux JUMP_TO_HANDLER_IF_JUNO_R(1) 20123d39dbcSSandrine Bailleux JUMP_TO_HANDLER_IF_JUNO_R(2) 20223d39dbcSSandrine Bailleux 20323d39dbcSSandrine Bailleux /* Board revision is not supported */ 204*a806dad5SJeenu Viswambharan no_ret plat_panic_handler 20523d39dbcSSandrine Bailleux 20685135283SDan Handleyendfunc plat_reset_handler 207371d4399SDavid Wang 208371d4399SDavid Wang /* ----------------------------------------------------- 2094c0d0390SSoby Mathew * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 210371d4399SDavid Wang * Helper function to calculate the core position. 211371d4399SDavid Wang * ----------------------------------------------------- 212371d4399SDavid Wang */ 213371d4399SDavid Wangfunc plat_arm_calc_core_pos 214371d4399SDavid Wang b css_calc_core_pos_swap_cluster 215371d4399SDavid Wangendfunc plat_arm_calc_core_pos 216