185135283SDan Handley/* 285135283SDan Handley * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 385135283SDan Handley * 485135283SDan Handley * Redistribution and use in source and binary forms, with or without 585135283SDan Handley * modification, are permitted provided that the following conditions are met: 685135283SDan Handley * 785135283SDan Handley * Redistributions of source code must retain the above copyright notice, this 885135283SDan Handley * list of conditions and the following disclaimer. 985135283SDan Handley * 1085135283SDan Handley * Redistributions in binary form must reproduce the above copyright notice, 1185135283SDan Handley * this list of conditions and the following disclaimer in the documentation 1285135283SDan Handley * and/or other materials provided with the distribution. 1385135283SDan Handley * 1485135283SDan Handley * Neither the name of ARM nor the names of its contributors may be used 1585135283SDan Handley * to endorse or promote products derived from this software without specific 1685135283SDan Handley * prior written permission. 1785135283SDan Handley * 1885135283SDan Handley * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1985135283SDan Handley * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2085135283SDan Handley * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2185135283SDan Handley * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2285135283SDan Handley * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2385135283SDan Handley * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2485135283SDan Handley * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2585135283SDan Handley * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2685135283SDan Handley * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2785135283SDan Handley * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2885135283SDan Handley * POSSIBILITY OF SUCH DAMAGE. 2985135283SDan Handley */ 3085135283SDan Handley 3185135283SDan Handley#include <arch.h> 3285135283SDan Handley#include <asm_macros.S> 3385135283SDan Handley#include <bl_common.h> 34*23d39dbcSSandrine Bailleux#include <cortex_a53.h> 3585135283SDan Handley#include <cortex_a57.h> 3685135283SDan Handley#include <v2m_def.h> 3785135283SDan Handley#include "../juno_def.h" 3885135283SDan Handley 3985135283SDan Handley 4085135283SDan Handley .globl plat_reset_handler 41371d4399SDavid Wang .globl plat_arm_calc_core_pos 4285135283SDan Handley 43*23d39dbcSSandrine Bailleux#define JUNO_REVISION(rev) REV_JUNO_R##rev 44*23d39dbcSSandrine Bailleux#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev 45*23d39dbcSSandrine Bailleux#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ 46*23d39dbcSSandrine Bailleux jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) 47*23d39dbcSSandrine Bailleux 4885135283SDan Handley /* -------------------------------------------------------------------- 49*23d39dbcSSandrine Bailleux * Helper macro to jump to the given handler if the board revision 50*23d39dbcSSandrine Bailleux * matches. 51*23d39dbcSSandrine Bailleux * Expects the Juno board revision in x0. 52*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 53*23d39dbcSSandrine Bailleux */ 54*23d39dbcSSandrine Bailleux .macro jump_to_handler _revision, _handler 55*23d39dbcSSandrine Bailleux cmp x0, #\_revision 56*23d39dbcSSandrine Bailleux b.eq \_handler 57*23d39dbcSSandrine Bailleux .endm 58*23d39dbcSSandrine Bailleux 59*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 60*23d39dbcSSandrine Bailleux * Helper macro that reads the part number of the current CPU and jumps 61*23d39dbcSSandrine Bailleux * to the given label if it matches the CPU MIDR provided. 6285135283SDan Handley * 63*23d39dbcSSandrine Bailleux * Clobbers x0. 64*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 65*23d39dbcSSandrine Bailleux */ 66*23d39dbcSSandrine Bailleux .macro jump_if_cpu_midr _cpu_midr, _label 67*23d39dbcSSandrine Bailleux mrs x0, midr_el1 68*23d39dbcSSandrine Bailleux ubfx x0, x0, MIDR_PN_SHIFT, #12 69*23d39dbcSSandrine Bailleux cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 70*23d39dbcSSandrine Bailleux b.eq \_label 71*23d39dbcSSandrine Bailleux .endm 72*23d39dbcSSandrine Bailleux 73*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 74*23d39dbcSSandrine Bailleux * Platform reset handler for Juno R0. 75*23d39dbcSSandrine Bailleux * 76*23d39dbcSSandrine Bailleux * Juno R0 has the following topology: 77*23d39dbcSSandrine Bailleux * - Quad core Cortex-A53 processor cluster; 78*23d39dbcSSandrine Bailleux * - Dual core Cortex-A57 processor cluster. 79*23d39dbcSSandrine Bailleux * 80*23d39dbcSSandrine Bailleux * This handler does the following: 8185135283SDan Handley * - Implement workaround for defect id 831273 by enabling an event 8285135283SDan Handley * stream every 65536 cycles. 8385135283SDan Handley * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 8485135283SDan Handley * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 85*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 86*23d39dbcSSandrine Bailleux */ 87*23d39dbcSSandrine Bailleuxfunc JUNO_HANDLER(0) 88*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 89*23d39dbcSSandrine Bailleux * Enable the event stream every 65536 cycles 90*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 91*23d39dbcSSandrine Bailleux */ 92*23d39dbcSSandrine Bailleux mov x0, #(0xf << EVNTI_SHIFT) 93*23d39dbcSSandrine Bailleux orr x0, x0, #EVNTEN_BIT 94*23d39dbcSSandrine Bailleux msr CNTKCTL_EL1, x0 95*23d39dbcSSandrine Bailleux 96*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 97*23d39dbcSSandrine Bailleux * Nothing else to do on Cortex-A53. 98*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 99*23d39dbcSSandrine Bailleux */ 100*23d39dbcSSandrine Bailleux jump_if_cpu_midr CORTEX_A53_MIDR, 1f 101*23d39dbcSSandrine Bailleux 102*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 103*23d39dbcSSandrine Bailleux * Cortex-A57 specific settings 104*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 105*23d39dbcSSandrine Bailleux */ 106*23d39dbcSSandrine Bailleux mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 107*23d39dbcSSandrine Bailleux (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) 108*23d39dbcSSandrine Bailleux msr L2CTLR_EL1, x0 109*23d39dbcSSandrine Bailleux1: 110*23d39dbcSSandrine Bailleux isb 111*23d39dbcSSandrine Bailleux ret 112*23d39dbcSSandrine Bailleuxendfunc JUNO_HANDLER(0) 113*23d39dbcSSandrine Bailleux 114*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 115*23d39dbcSSandrine Bailleux * Platform reset handler for Juno R1. 11685135283SDan Handley * 117*23d39dbcSSandrine Bailleux * Juno R1 has the following topology: 118*23d39dbcSSandrine Bailleux * - Quad core Cortex-A53 processor cluster; 119*23d39dbcSSandrine Bailleux * - Dual core Cortex-A57 processor cluster. 120*23d39dbcSSandrine Bailleux * 121*23d39dbcSSandrine Bailleux * This handler does the following: 12285135283SDan Handley * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 123*23d39dbcSSandrine Bailleux * 12485135283SDan Handley * Note that: 12585135283SDan Handley * - The default value for the L2 Tag RAM latency for Cortex-A57 is 12685135283SDan Handley * suitable. 127*23d39dbcSSandrine Bailleux * - Defect #831273 doesn't affect Juno R1. 12885135283SDan Handley * -------------------------------------------------------------------- 12985135283SDan Handley */ 130*23d39dbcSSandrine Bailleuxfunc JUNO_HANDLER(1) 13185135283SDan Handley /* -------------------------------------------------------------------- 132*23d39dbcSSandrine Bailleux * Nothing to do on Cortex-A53. 13385135283SDan Handley * -------------------------------------------------------------------- 13485135283SDan Handley */ 135*23d39dbcSSandrine Bailleux jump_if_cpu_midr CORTEX_A57_MIDR, A57 13685135283SDan Handley ret 13785135283SDan Handley 13885135283SDan HandleyA57: 13985135283SDan Handley /* -------------------------------------------------------------------- 14085135283SDan Handley * Cortex-A57 specific settings 14185135283SDan Handley * -------------------------------------------------------------------- 14285135283SDan Handley */ 143*23d39dbcSSandrine Bailleux mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) 14485135283SDan Handley msr L2CTLR_EL1, x0 14585135283SDan Handley isb 14685135283SDan Handley ret 147*23d39dbcSSandrine Bailleuxendfunc JUNO_HANDLER(1) 148*23d39dbcSSandrine Bailleux 149*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 150*23d39dbcSSandrine Bailleux * Platform reset handler for Juno R2. 151*23d39dbcSSandrine Bailleux * 152*23d39dbcSSandrine Bailleux * Juno R2 has the following topology: 153*23d39dbcSSandrine Bailleux * - Quad core Cortex-A53 processor cluster; 154*23d39dbcSSandrine Bailleux * - Dual core Cortex-A72 processor cluster. 155*23d39dbcSSandrine Bailleux * 156*23d39dbcSSandrine Bailleux * This handler does nothing. 157*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 158*23d39dbcSSandrine Bailleux */ 159*23d39dbcSSandrine Bailleuxfunc JUNO_HANDLER(2) 160*23d39dbcSSandrine Bailleux ret 161*23d39dbcSSandrine Bailleuxendfunc JUNO_HANDLER(2) 162*23d39dbcSSandrine Bailleux 163*23d39dbcSSandrine Bailleux /* -------------------------------------------------------------------- 164*23d39dbcSSandrine Bailleux * void plat_reset_handler(void); 165*23d39dbcSSandrine Bailleux * 166*23d39dbcSSandrine Bailleux * Determine the Juno board revision and call the appropriate reset 167*23d39dbcSSandrine Bailleux * handler. 168*23d39dbcSSandrine Bailleux * -------------------------------------------------------------------- 169*23d39dbcSSandrine Bailleux */ 170*23d39dbcSSandrine Bailleuxfunc plat_reset_handler 171*23d39dbcSSandrine Bailleux /* Read the V2M SYS_ID register */ 172*23d39dbcSSandrine Bailleux mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) 173*23d39dbcSSandrine Bailleux ldr w1, [x0] 174*23d39dbcSSandrine Bailleux /* Extract board revision from the SYS_ID */ 175*23d39dbcSSandrine Bailleux ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4 176*23d39dbcSSandrine Bailleux 177*23d39dbcSSandrine Bailleux JUMP_TO_HANDLER_IF_JUNO_R(0) 178*23d39dbcSSandrine Bailleux JUMP_TO_HANDLER_IF_JUNO_R(1) 179*23d39dbcSSandrine Bailleux JUMP_TO_HANDLER_IF_JUNO_R(2) 180*23d39dbcSSandrine Bailleux 181*23d39dbcSSandrine Bailleux /* Board revision is not supported */ 182*23d39dbcSSandrine Bailleuxnot_supported: 183*23d39dbcSSandrine Bailleux b not_supported 184*23d39dbcSSandrine Bailleux 18585135283SDan Handleyendfunc plat_reset_handler 186371d4399SDavid Wang 187371d4399SDavid Wang /* ----------------------------------------------------- 188371d4399SDavid Wang * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) 189371d4399SDavid Wang * Helper function to calculate the core position. 190371d4399SDavid Wang * ----------------------------------------------------- 191371d4399SDavid Wang */ 192371d4399SDavid Wangfunc plat_arm_calc_core_pos 193371d4399SDavid Wang b css_calc_core_pos_swap_cluster 194371d4399SDavid Wangendfunc plat_arm_calc_core_pos 195