1 /* 2 * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 #endif 58 59 /* 60 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 61 * max size of BL32 image. 62 */ 63 #if defined(SPD_spmd) 64 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 65 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 66 #endif 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* No SCP in FVP */ 72 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 73 74 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 75 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 76 77 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 78 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 79 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 80 81 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 82 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 83 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 84 85 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 86 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 87 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 88 89 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 90 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 91 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 92 93 /* Range of kernel DTB load address */ 94 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 95 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 96 97 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 98 FVP_DTB_DRAM_MAP_START, \ 99 FVP_DTB_DRAM_MAP_SIZE, \ 100 MT_MEMORY | MT_RO | MT_NS) 101 102 /* 103 * On the FVP platform when using the EL3 SPMC implementation allocate the 104 * datastore for tracking shared memory descriptors in the TZC DRAM section 105 * to ensure sufficient storage can be allocated. 106 * Provide an implementation of the accessor method to allow the datastore 107 * details to be retrieved by the SPMC. 108 * The SPMC will take care of initializing the memory region. 109 */ 110 111 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 112 113 #if SPMC_AT_EL3 114 /* 115 * Number of Secure Partitions supported. 116 * SPMC at EL3, uses this count to configure the maximum number of supported 117 * secure partitions. 118 */ 119 #define SECURE_PARTITION_COUNT 1 120 121 /* 122 * Number of Normal World Partitions supported. 123 * SPMC at EL3, uses this count to configure the maximum number of supported 124 * NWd partitions. 125 */ 126 #define NS_PARTITION_COUNT 1 127 128 /* 129 * Number of Logical Partitions supported. 130 * SPMC at EL3, uses this count to configure the maximum number of supported 131 * logical partitions. 132 */ 133 #define MAX_EL3_LP_DESCS_COUNT 1 134 135 #endif /* SPMC_AT_EL3 */ 136 137 /* 138 * Load address of BL33 for this platform port 139 */ 140 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 141 142 #if TRANSFER_LIST 143 #define FW_HANDOFF_SIZE 0x4000 144 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - FW_HANDOFF_SIZE) 145 #endif 146 147 /* 148 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 149 * plat_arm_mmap array defined for each BL stage. 150 */ 151 #if defined(IMAGE_BL31) 152 # if SPM_MM 153 # define PLAT_ARM_MMAP_ENTRIES 10 154 # define MAX_XLAT_TABLES 9 155 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 156 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 157 # elif SPMC_AT_EL3 158 # define PLAT_ARM_MMAP_ENTRIES 13 159 # define MAX_XLAT_TABLES 11 160 # else 161 # define PLAT_ARM_MMAP_ENTRIES 9 162 # if USE_DEBUGFS 163 # if ENABLE_RME 164 # define MAX_XLAT_TABLES 9 165 # else 166 # define MAX_XLAT_TABLES 8 167 # endif 168 # else 169 # if ENABLE_RME 170 # define MAX_XLAT_TABLES 8 171 # elif DRTM_SUPPORT 172 # define MAX_XLAT_TABLES 8 173 # else 174 # define MAX_XLAT_TABLES 7 175 # endif 176 # endif 177 # endif 178 #elif defined(IMAGE_BL32) 179 # if SPMC_AT_EL3 180 # define PLAT_ARM_MMAP_ENTRIES 270 181 # define MAX_XLAT_TABLES 10 182 # else 183 # define PLAT_ARM_MMAP_ENTRIES 9 184 # define MAX_XLAT_TABLES 6 185 # endif 186 #elif !USE_ROMLIB 187 # if ENABLE_RME && defined(IMAGE_BL2) 188 # define PLAT_ARM_MMAP_ENTRIES 12 189 # define MAX_XLAT_TABLES 6 190 # else 191 # define PLAT_ARM_MMAP_ENTRIES 11 192 # define MAX_XLAT_TABLES 5 193 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 194 #else 195 # define PLAT_ARM_MMAP_ENTRIES 12 196 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 197 defined(IMAGE_BL2) && MEASURED_BOOT 198 # define MAX_XLAT_TABLES 7 199 # else 200 # define MAX_XLAT_TABLES 6 201 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 202 #endif 203 204 /* 205 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 206 * plus a little space for growth. 207 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 208 * area. 209 */ 210 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO 211 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 212 #else 213 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 214 #endif 215 216 /* 217 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 218 */ 219 220 #if USE_ROMLIB 221 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 222 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 223 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 224 #else 225 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 226 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 227 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 228 #endif 229 230 /* 231 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 232 * Maximum size of BL2 increases as Trusted SRAM size increases. 233 */ 234 #if CRYPTO_SUPPORT 235 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 236 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 237 (2 * PAGE_SIZE) - \ 238 FVP_BL2_ROMLIB_OPTIMIZATION) 239 #else 240 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 241 (3 * PAGE_SIZE) - \ 242 FVP_BL2_ROMLIB_OPTIMIZATION) 243 #endif 244 #elif ARM_BL31_IN_DRAM 245 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 246 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 247 #else 248 /** 249 * Default to just under half of SRAM to ensure there's enough room for really 250 * large BL31 build configurations when using the default SRAM size (256 Kb). 251 */ 252 #define PLAT_ARM_MAX_BL2_SIZE \ 253 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 254 FVP_BL2_ROMLIB_OPTIMIZATION) 255 #endif 256 257 #if RESET_TO_BL31 258 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 259 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 260 ARM_SHARED_RAM_SIZE - \ 261 ARM_L0_GPT_SIZE) 262 #else 263 /* 264 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 265 * calculated using the current BL31 PROGBITS debug size plus the sizes of 266 * BL2 and BL1-RW. 267 * Size of the BL31 PROGBITS increases as the SRAM size increases. 268 */ 269 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 270 ARM_SHARED_RAM_SIZE - \ 271 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 272 #endif /* RESET_TO_BL31 */ 273 274 #ifndef __aarch64__ 275 #if RESET_TO_SP_MIN 276 /* Size of Trusted SRAM - the first 4KB of shared memory */ 277 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 278 ARM_SHARED_RAM_SIZE) 279 #else 280 /* 281 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 282 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 283 * BL2 and BL1-RW 284 */ 285 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 286 #endif /* RESET_TO_SP_MIN */ 287 #endif 288 289 /* 290 * Size of cacheable stacks 291 */ 292 #if defined(IMAGE_BL1) 293 # if CRYPTO_SUPPORT 294 # define PLATFORM_STACK_SIZE UL(0x1000) 295 # else 296 # define PLATFORM_STACK_SIZE UL(0x500) 297 # endif /* CRYPTO_SUPPORT */ 298 #elif defined(IMAGE_BL2) 299 # if CRYPTO_SUPPORT 300 # define PLATFORM_STACK_SIZE UL(0x1000) 301 # else 302 # define PLATFORM_STACK_SIZE UL(0x600) 303 # endif /* CRYPTO_SUPPORT */ 304 #elif defined(IMAGE_BL2U) 305 # define PLATFORM_STACK_SIZE UL(0x400) 306 #elif defined(IMAGE_BL31) 307 # if DRTM_SUPPORT 308 # define PLATFORM_STACK_SIZE UL(0x1000) 309 # else 310 # define PLATFORM_STACK_SIZE UL(0x800) 311 # endif /* DRTM_SUPPORT */ 312 #elif defined(IMAGE_BL32) 313 # if SPMC_AT_EL3 314 # define PLATFORM_STACK_SIZE UL(0x1000) 315 # else 316 # define PLATFORM_STACK_SIZE UL(0x440) 317 # endif /* SPMC_AT_EL3 */ 318 #elif defined(IMAGE_RMM) 319 # define PLATFORM_STACK_SIZE UL(0x440) 320 #endif 321 322 #define MAX_IO_DEVICES 3 323 #define MAX_IO_HANDLES 4 324 325 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 326 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 327 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 328 329 #if ARM_GPT_SUPPORT 330 /* 331 * Offset of the FIP in the GPT image. BL1 component uses this option 332 * as it does not load the partition table to get the FIP base 333 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 334 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 335 */ 336 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 337 #endif /* ARM_GPT_SUPPORT */ 338 339 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 340 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 341 342 /* 343 * PL011 related constants 344 */ 345 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 346 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 347 348 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 349 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 350 351 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 352 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 353 354 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 355 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 356 357 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 358 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 359 360 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 361 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 362 363 /* CCI related constants */ 364 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 365 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 366 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 367 368 /* CCI-500/CCI-550 on Base platform */ 369 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 370 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 371 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 372 373 /* CCN related constants. Only CCN 502 is currently supported */ 374 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 375 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 376 377 /* System timer related constants */ 378 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 379 380 /* Mailbox base address */ 381 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 382 383 384 /* TrustZone controller related constants 385 * 386 * Currently only filters 0 and 2 are connected on Base FVP. 387 * Filter 0 : CPU clusters (no access to DRAM by default) 388 * Filter 1 : not connected 389 * Filter 2 : LCDs (access to VRAM allowed by default) 390 * Filter 3 : not connected 391 * Programming unconnected filters will have no effect at the 392 * moment. These filter could, however, be connected in future. 393 * So care should be taken not to configure the unused filters. 394 * 395 * Allow only non-secure access to all DRAM to supported devices. 396 * Give access to the CPUs and Virtio. Some devices 397 * would normally use the default ID so allow that too. 398 */ 399 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 400 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 401 402 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 403 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 404 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 405 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 406 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 407 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 408 409 /* 410 * GIC related constants to cater for both GICv2 and GICv3 instances of an 411 * FVP. They could be overridden at runtime in case the FVP implements the 412 * legacy VE memory map. 413 */ 414 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 415 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 416 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 417 418 /* 419 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 420 * terminology. On a GICv2 system or mode, the lists will be merged and treated 421 * as Group 0 interrupts. 422 */ 423 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 424 ARM_G1S_IRQ_PROPS(grp), \ 425 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 426 GIC_INTR_CFG_LEVEL), \ 427 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 428 GIC_INTR_CFG_LEVEL) 429 430 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 431 432 #if SDEI_IN_FCONF 433 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 434 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 435 #else 436 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 437 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 438 ARM_SDEI_PRIVATE_EVENTS, \ 439 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 440 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 441 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 442 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 443 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 444 #else 445 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 446 #endif 447 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 448 #endif 449 450 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 451 PLAT_SP_IMAGE_NS_BUF_SIZE) 452 453 #define PLAT_SP_PRI 0x20 454 455 /* 456 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 457 */ 458 #ifdef __aarch64__ 459 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 460 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 461 #else 462 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 463 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 464 #endif 465 466 /* 467 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 468 */ 469 #if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) 470 /* Account for additional measurements of secure partitions and SPM. */ 471 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 472 #else 473 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 474 #endif 475 476 /* 477 * Maximum size of Event Log buffer used for DRTM 478 */ 479 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 480 481 /* 482 * Number of MMAP entries used by DRTM implementation 483 */ 484 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 485 486 #endif /* PLATFORM_DEF_H */ 487