1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 /* virtual address used by dynamic mem_protect for chunk_base */ 47 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 48 49 /* No SCP in FVP */ 50 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 51 52 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 53 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 54 55 /* 56 * Load address of BL33 for this platform port 57 */ 58 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 59 60 /* 61 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 62 * plat_arm_mmap array defined for each BL stage. 63 */ 64 #if defined(IMAGE_BL31) 65 # if SPM_MM 66 # define PLAT_ARM_MMAP_ENTRIES 9 67 # define MAX_XLAT_TABLES 9 68 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 69 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 70 # else 71 # define PLAT_ARM_MMAP_ENTRIES 8 72 # if USE_DEBUGFS 73 # define MAX_XLAT_TABLES 6 74 # else 75 # define MAX_XLAT_TABLES 5 76 # endif 77 # endif 78 #elif defined(IMAGE_BL32) 79 # define PLAT_ARM_MMAP_ENTRIES 8 80 # define MAX_XLAT_TABLES 5 81 #elif !USE_ROMLIB 82 # define PLAT_ARM_MMAP_ENTRIES 11 83 # define MAX_XLAT_TABLES 5 84 #else 85 # define PLAT_ARM_MMAP_ENTRIES 12 86 # define MAX_XLAT_TABLES 6 87 #endif 88 89 /* 90 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 91 * plus a little space for growth. 92 */ 93 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 94 95 /* 96 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 97 */ 98 99 #if USE_ROMLIB 100 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 101 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 102 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) 103 #else 104 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 105 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 106 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 107 #endif 108 109 /* 110 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 111 * little space for growth. 112 */ 113 #if TRUSTED_BOARD_BOOT 114 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 115 #else 116 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) 117 #endif 118 119 #if RESET_TO_BL31 120 /* Size of Trusted SRAM - the first 4KB of shared memory */ 121 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 122 ARM_SHARED_RAM_SIZE) 123 #else 124 /* 125 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 126 * calculated using the current BL31 PROGBITS debug size plus the sizes of 127 * BL2 and BL1-RW 128 */ 129 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 130 #endif /* RESET_TO_BL31 */ 131 132 #ifndef __aarch64__ 133 /* 134 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 135 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 136 * BL2 and BL1-RW 137 */ 138 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 139 #endif 140 141 /* 142 * Size of cacheable stacks 143 */ 144 #if defined(IMAGE_BL1) 145 # if TRUSTED_BOARD_BOOT 146 # define PLATFORM_STACK_SIZE UL(0x1000) 147 # else 148 # define PLATFORM_STACK_SIZE UL(0x500) 149 # endif 150 #elif defined(IMAGE_BL2) 151 # if TRUSTED_BOARD_BOOT 152 # define PLATFORM_STACK_SIZE UL(0x1000) 153 # else 154 # define PLATFORM_STACK_SIZE UL(0x440) 155 # endif 156 #elif defined(IMAGE_BL2U) 157 # define PLATFORM_STACK_SIZE UL(0x400) 158 #elif defined(IMAGE_BL31) 159 # define PLATFORM_STACK_SIZE UL(0x800) 160 #elif defined(IMAGE_BL32) 161 # define PLATFORM_STACK_SIZE UL(0x440) 162 #endif 163 164 #define MAX_IO_DEVICES 3 165 #define MAX_IO_HANDLES 4 166 167 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 168 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 169 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 170 171 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 172 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 173 174 /* 175 * PL011 related constants 176 */ 177 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 178 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 179 180 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 181 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 182 183 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 184 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 185 186 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 187 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 188 189 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 190 191 /* CCI related constants */ 192 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 193 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 194 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 195 196 /* CCI-500/CCI-550 on Base platform */ 197 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 198 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 199 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 200 201 /* CCN related constants. Only CCN 502 is currently supported */ 202 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 203 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 204 205 /* System timer related constants */ 206 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 207 208 /* Mailbox base address */ 209 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 210 211 212 /* TrustZone controller related constants 213 * 214 * Currently only filters 0 and 2 are connected on Base FVP. 215 * Filter 0 : CPU clusters (no access to DRAM by default) 216 * Filter 1 : not connected 217 * Filter 2 : LCDs (access to VRAM allowed by default) 218 * Filter 3 : not connected 219 * Programming unconnected filters will have no effect at the 220 * moment. These filter could, however, be connected in future. 221 * So care should be taken not to configure the unused filters. 222 * 223 * Allow only non-secure access to all DRAM to supported devices. 224 * Give access to the CPUs and Virtio. Some devices 225 * would normally use the default ID so allow that too. 226 */ 227 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 228 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 229 230 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 231 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 232 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 233 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 234 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 235 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 236 237 /* 238 * GIC related constants to cater for both GICv2 and GICv3 instances of an 239 * FVP. They could be overriden at runtime in case the FVP implements the legacy 240 * VE memory map. 241 */ 242 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 243 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 244 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 245 246 /* 247 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 248 * terminology. On a GICv2 system or mode, the lists will be merged and treated 249 * as Group 0 interrupts. 250 */ 251 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 252 ARM_G1S_IRQ_PROPS(grp), \ 253 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 254 GIC_INTR_CFG_LEVEL), \ 255 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 256 GIC_INTR_CFG_LEVEL) 257 258 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 259 260 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 261 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 262 263 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 264 PLAT_SP_IMAGE_NS_BUF_SIZE) 265 266 #define PLAT_SP_PRI PLAT_RAS_PRI 267 268 /* 269 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 270 */ 271 #ifdef __aarch64__ 272 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 273 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 274 #else 275 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 276 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 277 #endif 278 279 #endif /* PLATFORM_DEF_H */ 280