1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 /* Protected physical address size */ 59 #define PLAT_ARM_PPS (SZ_1T) 60 #endif /* ENABLE_RME */ 61 62 /* 63 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 64 * max size of BL32 image. 65 */ 66 #if defined(SPD_spmd) 67 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 68 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 69 #endif 70 71 /* Virtual address used by dynamic mem_protect for chunk_base */ 72 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 73 74 /* No SCP in FVP */ 75 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 76 77 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 78 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 79 80 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 81 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 82 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 83 84 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 85 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 86 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 87 88 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 89 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 90 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 91 92 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 93 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 94 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 95 96 /* 97 * On the FVP platform when using the EL3 SPMC implementation allocate the 98 * datastore for tracking shared memory descriptors in the TZC DRAM section 99 * to ensure sufficient storage can be allocated. 100 * Provide an implementation of the accessor method to allow the datastore 101 * details to be retrieved by the SPMC. 102 * The SPMC will take care of initializing the memory region. 103 */ 104 105 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 106 107 /* Define memory configuration for device tree files. */ 108 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 109 110 #if SPMC_AT_EL3 111 112 /* Define maximum size of sp manifest file. */ 113 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE U(0x1000) 114 115 /* 116 * Number of Secure Partitions supported. 117 * SPMC at EL3, uses this count to configure the maximum number of supported 118 * secure partitions. 119 */ 120 #define SECURE_PARTITION_COUNT 1 121 122 /* 123 * Number of Normal World Partitions supported. 124 * SPMC at EL3, uses this count to configure the maximum number of supported 125 * NWd partitions. 126 */ 127 #define NS_PARTITION_COUNT 1 128 129 /* 130 * Number of Logical Partitions supported. 131 * SPMC at EL3, uses this count to configure the maximum number of supported 132 * logical partitions. 133 */ 134 #define MAX_EL3_LP_DESCS_COUNT 1 135 136 #else /* !SPMC_AT_EL3 */ 137 138 /* Define maximum size of sp manifest file. */ 139 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE U(0x0) 140 141 #endif /* SPMC_AT_EL3 */ 142 143 /* 144 * Load address of BL33 for this platform port 145 */ 146 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 147 148 #if TRANSFER_LIST 149 #if SPMC_AT_EL3 150 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x6000) 151 #else 152 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000) 153 #endif 154 155 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 156 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 157 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 158 159 #if RESET_TO_BL31 160 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 161 #endif 162 163 #else 164 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 165 #endif 166 167 /* 168 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 169 * plat_arm_mmap array defined for each BL stage. 170 */ 171 #if defined(IMAGE_BL31) 172 # if SPM_MM 173 # define PLAT_ARM_MMAP_ENTRIES 10 174 # define MAX_XLAT_TABLES 9 175 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 176 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 177 # elif SPMC_AT_EL3 178 # define PLAT_ARM_MMAP_ENTRIES 13 179 # define MAX_XLAT_TABLES 11 180 # define PLAT_SP_IMAGE_MMAP_REGIONS 31 181 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 13 182 # else 183 # define PLAT_ARM_MMAP_ENTRIES 9 184 # if USE_DEBUGFS 185 # if ENABLE_RME 186 # define MAX_XLAT_TABLES 9 187 # else 188 # define MAX_XLAT_TABLES 8 189 # endif 190 # else 191 # if ENABLE_RME 192 # define MAX_XLAT_TABLES 8 193 # elif DRTM_SUPPORT 194 # define MAX_XLAT_TABLES 8 195 # else 196 # define MAX_XLAT_TABLES 7 197 # endif 198 # endif 199 # endif 200 #elif defined(IMAGE_BL32) 201 # if SPMC_AT_EL3 202 # define PLAT_ARM_MMAP_ENTRIES 270 203 # define MAX_XLAT_TABLES 10 204 # else 205 # define PLAT_ARM_MMAP_ENTRIES 9 206 # define MAX_XLAT_TABLES 6 207 # endif 208 #elif !USE_ROMLIB 209 # if defined(IMAGE_BL2) && (ENABLE_RME || SPMC_AT_EL3) 210 # define PLAT_ARM_MMAP_ENTRIES 12 211 # define MAX_XLAT_TABLES 6 212 # else 213 # define PLAT_ARM_MMAP_ENTRIES 12 214 # define MAX_XLAT_TABLES 5 215 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 216 #else 217 # define PLAT_ARM_MMAP_ENTRIES 12 218 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 219 defined(IMAGE_BL2) && MEASURED_BOOT 220 # define MAX_XLAT_TABLES 7 221 # else 222 # define MAX_XLAT_TABLES 6 223 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 224 #endif 225 226 /* 227 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 228 * plus a little space for growth. 229 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 230 * area. 231 */ 232 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 233 FVP_TRUSTED_SRAM_SIZE == 512 234 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 235 #else 236 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 237 #endif 238 239 /* 240 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 241 */ 242 243 #if USE_ROMLIB 244 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 245 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 246 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 247 #else 248 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 249 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 250 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 251 #endif 252 253 /* 254 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 255 * Maximum size of BL2 increases as Trusted SRAM size increases. 256 */ 257 #if CRYPTO_SUPPORT 258 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 259 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 260 (2 * PAGE_SIZE) - \ 261 FVP_BL2_ROMLIB_OPTIMIZATION) 262 #else 263 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 264 (3 * PAGE_SIZE) - \ 265 FVP_BL2_ROMLIB_OPTIMIZATION) 266 #endif 267 #elif ARM_BL31_IN_DRAM 268 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 269 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 270 #else 271 /** 272 * Default to just under half of SRAM to ensure there's enough room for really 273 * large BL31 build configurations when using the default SRAM size (256 Kb). 274 */ 275 #define PLAT_ARM_MAX_BL2_SIZE \ 276 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 277 FVP_BL2_ROMLIB_OPTIMIZATION) 278 #endif 279 280 #if RESET_TO_BL31 281 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 282 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 283 ARM_SHARED_RAM_SIZE - \ 284 ARM_L0_GPT_SIZE) 285 #else 286 /* 287 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 288 * calculated using the current BL31 PROGBITS debug size plus the sizes of 289 * BL2 and BL1-RW. 290 * Size of the BL31 PROGBITS increases as the SRAM size increases. 291 */ 292 #if TRANSFER_LIST 293 #define PLAT_ARM_MAX_BL31_SIZE \ 294 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 295 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 296 #else 297 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 298 ARM_SHARED_RAM_SIZE - \ 299 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 300 #endif /* TRANSFER_LIST */ 301 #endif /* RESET_TO_BL31 */ 302 303 #ifndef __aarch64__ 304 #if RESET_TO_SP_MIN 305 /* Size of Trusted SRAM - the first 4KB of shared memory */ 306 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 307 ARM_SHARED_RAM_SIZE) 308 #else 309 /* 310 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 311 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 312 * BL2 and BL1-RW 313 */ 314 #if TRANSFER_LIST 315 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 316 ARM_SHARED_RAM_SIZE - \ 317 PLAT_ARM_FW_HANDOFF_SIZE) 318 #else 319 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 320 ARM_SHARED_RAM_SIZE - \ 321 ARM_FW_CONFIGS_SIZE) 322 #endif /* TRANSFER_LIST */ 323 #endif /* RESET_TO_SP_MIN */ 324 #endif 325 326 /* 327 * Size of cacheable stacks 328 */ 329 #if defined(IMAGE_BL1) 330 # if CRYPTO_SUPPORT 331 # define PLATFORM_STACK_SIZE UL(0x1000) 332 # else 333 # define PLATFORM_STACK_SIZE UL(0x500) 334 # endif /* CRYPTO_SUPPORT */ 335 #elif defined(IMAGE_BL2) 336 # if CRYPTO_SUPPORT 337 # define PLATFORM_STACK_SIZE UL(0x1000) 338 # else 339 # define PLATFORM_STACK_SIZE UL(0x600) 340 # endif /* CRYPTO_SUPPORT */ 341 #elif defined(IMAGE_BL2U) 342 # define PLATFORM_STACK_SIZE UL(0x400) 343 #elif defined(IMAGE_BL31) 344 # if DRTM_SUPPORT 345 # define PLATFORM_STACK_SIZE UL(0x1000) 346 # else 347 # define PLATFORM_STACK_SIZE UL(0x800) 348 # endif /* DRTM_SUPPORT */ 349 #elif defined(IMAGE_BL32) 350 # if SPMC_AT_EL3 351 # define PLATFORM_STACK_SIZE UL(0x1000) 352 # else 353 # define PLATFORM_STACK_SIZE UL(0x440) 354 # endif /* SPMC_AT_EL3 */ 355 #elif defined(IMAGE_RMM) 356 # define PLATFORM_STACK_SIZE UL(0x440) 357 #endif 358 359 #define MAX_IO_DEVICES 3 360 #define MAX_IO_HANDLES 4 361 362 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 363 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 364 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 365 366 #if ARM_GPT_SUPPORT 367 /* 368 * Offset of the FIP in the GPT image. BL1 component uses this option 369 * as it does not load the partition table to get the FIP base 370 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 371 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 372 */ 373 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 374 #endif /* ARM_GPT_SUPPORT */ 375 376 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 377 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 378 379 /* 380 * PL011 related constants 381 */ 382 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 383 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 384 385 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 386 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 387 388 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 389 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 390 391 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 392 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 393 394 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 395 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 396 397 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 398 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 399 400 /* CCI related constants */ 401 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 402 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 403 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 404 405 /* CCI-500/CCI-550 on Base platform */ 406 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 407 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 408 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 409 410 /* CCN related constants. Only CCN 502 is currently supported */ 411 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 412 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 413 414 /* System timer related constants */ 415 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 416 417 /* Mailbox base address */ 418 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 419 420 /* PCIe memory region 1 (Base Platform RevC only) */ 421 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 422 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 423 424 /* 425 * PCIe memory region 2 (Base Platform RevC only) 426 * The full size of the second PCI memory region is 256GB 427 * but for now we only allocate the L1 GPTs for the first 3GB. 428 */ 429 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 430 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 431 432 /* TrustZone controller related constants 433 * 434 * Currently only filters 0 and 2 are connected on Base FVP. 435 * Filter 0 : CPU clusters (no access to DRAM by default) 436 * Filter 1 : not connected 437 * Filter 2 : LCDs (access to VRAM allowed by default) 438 * Filter 3 : not connected 439 * Programming unconnected filters will have no effect at the 440 * moment. These filter could, however, be connected in future. 441 * So care should be taken not to configure the unused filters. 442 * 443 * Allow only non-secure access to all DRAM to supported devices. 444 * Give access to the CPUs and Virtio. Some devices 445 * would normally use the default ID so allow that too. 446 */ 447 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 448 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 449 450 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 451 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 452 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 453 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 454 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 455 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 456 457 /* 458 * GIC related constants to cater for both GICv2 and GICv3 instances of an 459 * FVP. They could be overridden at runtime in case the FVP implements the 460 * legacy VE memory map. 461 */ 462 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 463 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 464 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 465 466 /* 467 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 468 * terminology. On a GICv2 system or mode, the lists will be merged and treated 469 * as Group 0 interrupts. 470 */ 471 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 472 ARM_G1S_IRQ_PROPS(grp), \ 473 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 474 GIC_INTR_CFG_LEVEL), \ 475 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 476 GIC_INTR_CFG_LEVEL) 477 478 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 479 480 #if SDEI_IN_FCONF 481 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 482 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 483 #else 484 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 485 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 486 ARM_SDEI_PRIVATE_EVENTS, \ 487 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 488 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 489 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 490 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 491 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 492 #else 493 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 494 #endif 495 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 496 #endif 497 498 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 499 PLAT_SPM_BUF_SIZE) 500 501 #define PLAT_SP_PRI 0x20 502 503 /* 504 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 505 */ 506 #ifdef __aarch64__ 507 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 508 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 509 #else 510 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 511 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 512 #endif 513 514 /* 515 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 516 * TODO: calculate maximum EventLog size using the calculation: 517 * Maximum size of Event Log * Number of images 518 */ 519 #if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed))) 520 /* 521 * Account for additional measurements of secure partitions and SPM. 522 * Also, account for OP-TEE running with maximum number of SPs. 523 */ 524 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 525 #elif defined(IMAGE_BL1) && TRANSFER_LIST 526 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 527 #else 528 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 529 #endif 530 531 /* 532 * Maximum size of Event Log buffer used for DRTM 533 */ 534 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 535 536 /* 537 * Number of MMAP entries used by DRTM implementation 538 */ 539 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 540 541 #endif /* PLATFORM_DEF_H */ 542