1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && (RESET_TO_BL31 || (ENABLE_SPM && !SPM_DEPRECATED)) 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 #include <drivers/arm/tzc400.h> 22 #include <lib/utils_def.h> 23 #include <plat/common/common_def.h> 24 25 #include <arm_def.h> 26 #include <arm_spm_def.h> 27 #include <v2m_def.h> 28 29 #include "../fvp_def.h" 30 31 /* Required platform porting definitions */ 32 #define PLATFORM_CORE_COUNT \ 33 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 34 35 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 36 PLATFORM_CORE_COUNT) + 1 37 38 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 39 40 /* 41 * Other platform porting definitions are provided by included headers 42 */ 43 44 /* 45 * Required ARM standard platform porting definitions 46 */ 47 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 48 49 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 50 51 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 52 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 53 54 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 55 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 56 57 /* virtual address used by dynamic mem_protect for chunk_base */ 58 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 59 60 /* No SCP in FVP */ 61 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 62 63 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 64 65 /* 66 * Load address of BL33 for this platform port 67 */ 68 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) 69 70 /* 71 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 72 * plat_arm_mmap array defined for each BL stage. 73 */ 74 #if defined(IMAGE_BL31) 75 # if ENABLE_SPM 76 # define PLAT_ARM_MMAP_ENTRIES 9 77 # define MAX_XLAT_TABLES 9 78 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 79 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 80 # else 81 # define PLAT_ARM_MMAP_ENTRIES 8 82 # define MAX_XLAT_TABLES 5 83 # endif 84 #elif defined(IMAGE_BL32) 85 # define PLAT_ARM_MMAP_ENTRIES 8 86 # define MAX_XLAT_TABLES 5 87 #elif !USE_ROMLIB 88 # define PLAT_ARM_MMAP_ENTRIES 11 89 # define MAX_XLAT_TABLES 5 90 #else 91 # define PLAT_ARM_MMAP_ENTRIES 12 92 # define MAX_XLAT_TABLES 6 93 #endif 94 95 /* 96 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 97 * plus a little space for growth. 98 */ 99 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 100 101 /* 102 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 103 */ 104 105 #if USE_ROMLIB 106 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 107 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 108 #else 109 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 110 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 111 #endif 112 113 /* 114 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 115 * little space for growth. 116 */ 117 #if TRUSTED_BOARD_BOOT 118 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 119 #else 120 # define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) 121 #endif 122 123 /* 124 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 125 * calculated using the current BL31 PROGBITS debug size plus the sizes of 126 * BL2 and BL1-RW 127 */ 128 #if ENABLE_SPM && !SPM_DEPRECATED 129 #define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) 130 #else 131 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 132 #endif 133 134 #ifdef AARCH32 135 /* 136 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 137 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 138 * BL2 and BL1-RW 139 */ 140 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 141 #endif 142 143 /* 144 * Size of cacheable stacks 145 */ 146 #if defined(IMAGE_BL1) 147 # if TRUSTED_BOARD_BOOT 148 # define PLATFORM_STACK_SIZE UL(0x1000) 149 # else 150 # define PLATFORM_STACK_SIZE UL(0x440) 151 # endif 152 #elif defined(IMAGE_BL2) 153 # if TRUSTED_BOARD_BOOT 154 # define PLATFORM_STACK_SIZE UL(0x1000) 155 # else 156 # define PLATFORM_STACK_SIZE UL(0x400) 157 # endif 158 #elif defined(IMAGE_BL2U) 159 # define PLATFORM_STACK_SIZE UL(0x400) 160 #elif defined(IMAGE_BL31) 161 # if ENABLE_SPM 162 # define PLATFORM_STACK_SIZE UL(0x600) 163 # elif PLAT_XLAT_TABLES_DYNAMIC 164 # define PLATFORM_STACK_SIZE UL(0x800) 165 # else 166 # define PLATFORM_STACK_SIZE UL(0x400) 167 # endif 168 #elif defined(IMAGE_BL32) 169 # define PLATFORM_STACK_SIZE UL(0x440) 170 #endif 171 172 #define MAX_IO_DEVICES 3 173 #define MAX_IO_HANDLES 4 174 175 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 176 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 177 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 178 179 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 180 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 181 182 /* 183 * PL011 related constants 184 */ 185 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 186 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 187 188 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 189 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 190 191 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 192 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 193 194 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 195 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 196 197 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 198 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 199 200 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 201 202 /* CCI related constants */ 203 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 204 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 205 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 206 207 /* CCI-500/CCI-550 on Base platform */ 208 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 209 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 210 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 211 212 /* CCN related constants. Only CCN 502 is currently supported */ 213 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 214 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 215 216 /* System timer related constants */ 217 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 218 219 /* Mailbox base address */ 220 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 221 222 223 /* TrustZone controller related constants 224 * 225 * Currently only filters 0 and 2 are connected on Base FVP. 226 * Filter 0 : CPU clusters (no access to DRAM by default) 227 * Filter 1 : not connected 228 * Filter 2 : LCDs (access to VRAM allowed by default) 229 * Filter 3 : not connected 230 * Programming unconnected filters will have no effect at the 231 * moment. These filter could, however, be connected in future. 232 * So care should be taken not to configure the unused filters. 233 * 234 * Allow only non-secure access to all DRAM to supported devices. 235 * Give access to the CPUs and Virtio. Some devices 236 * would normally use the default ID so allow that too. 237 */ 238 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 239 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 240 241 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 242 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 243 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 244 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 245 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 246 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 247 248 /* 249 * GIC related constants to cater for both GICv2 and GICv3 instances of an 250 * FVP. They could be overriden at runtime in case the FVP implements the legacy 251 * VE memory map. 252 */ 253 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 254 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 255 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 256 257 /* 258 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 259 * terminology. On a GICv2 system or mode, the lists will be merged and treated 260 * as Group 0 interrupts. 261 */ 262 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 263 ARM_G1S_IRQ_PROPS(grp), \ 264 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 265 GIC_INTR_CFG_LEVEL), \ 266 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 267 GIC_INTR_CFG_LEVEL) 268 269 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 270 271 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 272 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 273 274 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 275 PLAT_SP_IMAGE_NS_BUF_SIZE) 276 277 #define PLAT_SP_PRI PLAT_RAS_PRI 278 279 #endif /* PLATFORM_DEF_H */ 280