1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arm_def.h> 35 #include <board_arm_def.h> 36 #include <common_def.h> 37 #include <tzc400.h> 38 #include <utils.h> 39 #include <v2m_def.h> 40 #include "../fvp_def.h" 41 42 /* Required platform porting definitions */ 43 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 44 PLATFORM_CORE_COUNT) 45 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 46 #define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER) 47 48 /* 49 * Other platform porting definitions are provided by included headers 50 */ 51 52 /* 53 * Required ARM standard platform porting definitions 54 */ 55 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 56 57 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 58 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 59 60 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 61 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 62 63 /* No SCP in FVP */ 64 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 65 66 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) 67 68 /* 69 * Load address of BL33 for this platform port 70 */ 71 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) 72 73 74 /* 75 * PL011 related constants 76 */ 77 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 78 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 79 80 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 81 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 82 83 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 84 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 85 86 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 87 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 88 89 /* CCI related constants */ 90 #define PLAT_ARM_CCI_BASE 0x2c090000 91 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 92 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 93 94 /* CCN related constants. Only CCN 502 is currently supported */ 95 #define PLAT_ARM_CCN_BASE 0x2e000000 96 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 97 98 /* System timer related constants */ 99 #define PLAT_ARM_NSTIMER_FRAME_ID 1 100 101 /* Mailbox base address */ 102 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 103 104 105 /* TrustZone controller related constants 106 * 107 * Currently only filters 0 and 2 are connected on Base FVP. 108 * Filter 0 : CPU clusters (no access to DRAM by default) 109 * Filter 1 : not connected 110 * Filter 2 : LCDs (access to VRAM allowed by default) 111 * Filter 3 : not connected 112 * Programming unconnected filters will have no effect at the 113 * moment. These filter could, however, be connected in future. 114 * So care should be taken not to configure the unused filters. 115 * 116 * Allow only non-secure access to all DRAM to supported devices. 117 * Give access to the CPUs and Virtio. Some devices 118 * would normally use the default ID so allow that too. 119 */ 120 #define PLAT_ARM_TZC_BASE 0x2a4a0000 121 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 122 123 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 124 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 125 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 126 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 127 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 128 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 129 130 /* 131 * GIC related constants to cater for both GICv2 and GICv3 instances of an 132 * FVP. They could be overriden at runtime in case the FVP implements the legacy 133 * VE memory map. 134 */ 135 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 136 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 137 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 138 139 /* 140 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 141 * terminology. On a GICv2 system or mode, the lists will be merged and treated 142 * as Group 0 interrupts. 143 */ 144 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 145 FVP_IRQ_TZ_WDOG, \ 146 FVP_IRQ_SEC_SYS_TIMER 147 148 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 149 150 #endif /* __PLATFORM_DEF_H__ */ 151