1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 #include <arm_def.h> 22 #include <arm_spm_def.h> 23 #include <common_def.h> 24 #include <tzc400.h> 25 #include <utils_def.h> 26 #include <v2m_def.h> 27 #include "../fvp_def.h" 28 29 /* Required platform porting definitions */ 30 #define PLATFORM_CORE_COUNT \ 31 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 32 33 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 34 PLATFORM_CORE_COUNT) + 1 35 36 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 37 38 /* 39 * Other platform porting definitions are provided by included headers 40 */ 41 42 /* 43 * Required ARM standard platform porting definitions 44 */ 45 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 46 47 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 48 49 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 50 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 51 52 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 53 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 54 55 /* virtual address used by dynamic mem_protect for chunk_base */ 56 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 57 58 /* No SCP in FVP */ 59 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 60 61 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 62 63 /* 64 * Load address of BL33 for this platform port 65 */ 66 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) 67 68 /* 69 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 70 * plat_arm_mmap array defined for each BL stage. 71 */ 72 #if defined(IMAGE_BL31) 73 # if ENABLE_SPM 74 # define PLAT_ARM_MMAP_ENTRIES 9 75 # define MAX_XLAT_TABLES 7 76 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 77 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 78 # else 79 # define PLAT_ARM_MMAP_ENTRIES 8 80 # define MAX_XLAT_TABLES 5 81 # endif 82 #elif defined(IMAGE_BL32) 83 # define PLAT_ARM_MMAP_ENTRIES 8 84 # define MAX_XLAT_TABLES 5 85 #elif !USE_ROMLIB 86 # define PLAT_ARM_MMAP_ENTRIES 11 87 # define MAX_XLAT_TABLES 5 88 #else 89 # define PLAT_ARM_MMAP_ENTRIES 12 90 # define MAX_XLAT_TABLES 6 91 #endif 92 93 /* 94 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 95 * plus a little space for growth. 96 */ 97 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 98 99 /* 100 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 101 */ 102 103 #if USE_ROMLIB 104 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 105 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 106 #else 107 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 108 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 109 #endif 110 111 /* 112 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 113 * little space for growth. 114 */ 115 #if TRUSTED_BOARD_BOOT 116 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 117 #else 118 # define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) 119 #endif 120 121 /* 122 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 123 * calculated using the current BL31 PROGBITS debug size plus the sizes of 124 * BL2 and BL1-RW 125 */ 126 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 127 128 #ifdef AARCH32 129 /* 130 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 131 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 132 * BL2 and BL1-RW 133 */ 134 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 135 #endif 136 137 /* 138 * Size of cacheable stacks 139 */ 140 #if defined(IMAGE_BL1) 141 # if TRUSTED_BOARD_BOOT 142 # define PLATFORM_STACK_SIZE UL(0x1000) 143 # else 144 # define PLATFORM_STACK_SIZE UL(0x440) 145 # endif 146 #elif defined(IMAGE_BL2) 147 # if TRUSTED_BOARD_BOOT 148 # define PLATFORM_STACK_SIZE UL(0x1000) 149 # else 150 # define PLATFORM_STACK_SIZE UL(0x400) 151 # endif 152 #elif defined(IMAGE_BL2U) 153 # define PLATFORM_STACK_SIZE UL(0x400) 154 #elif defined(IMAGE_BL31) 155 # if ENABLE_SPM 156 # define PLATFORM_STACK_SIZE UL(0x500) 157 # elif PLAT_XLAT_TABLES_DYNAMIC 158 # define PLATFORM_STACK_SIZE UL(0x800) 159 # else 160 # define PLATFORM_STACK_SIZE UL(0x400) 161 # endif 162 #elif defined(IMAGE_BL32) 163 # define PLATFORM_STACK_SIZE UL(0x440) 164 #endif 165 166 #define MAX_IO_DEVICES 3 167 #define MAX_IO_HANDLES 4 168 169 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 170 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 171 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 172 173 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 174 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 175 176 /* 177 * PL011 related constants 178 */ 179 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 180 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 181 182 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 183 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 184 185 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 186 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 187 188 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 189 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 190 191 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 192 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 193 194 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 195 196 /* CCI related constants */ 197 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 198 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 199 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 200 201 /* CCI-500/CCI-550 on Base platform */ 202 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 203 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 204 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 205 206 /* CCN related constants. Only CCN 502 is currently supported */ 207 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 208 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 209 210 /* System timer related constants */ 211 #define PLAT_ARM_NSTIMER_FRAME_ID 1 212 213 /* Mailbox base address */ 214 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 215 216 217 /* TrustZone controller related constants 218 * 219 * Currently only filters 0 and 2 are connected on Base FVP. 220 * Filter 0 : CPU clusters (no access to DRAM by default) 221 * Filter 1 : not connected 222 * Filter 2 : LCDs (access to VRAM allowed by default) 223 * Filter 3 : not connected 224 * Programming unconnected filters will have no effect at the 225 * moment. These filter could, however, be connected in future. 226 * So care should be taken not to configure the unused filters. 227 * 228 * Allow only non-secure access to all DRAM to supported devices. 229 * Give access to the CPUs and Virtio. Some devices 230 * would normally use the default ID so allow that too. 231 */ 232 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 233 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 234 235 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 236 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 237 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 238 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 239 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 240 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 241 242 /* 243 * GIC related constants to cater for both GICv2 and GICv3 instances of an 244 * FVP. They could be overriden at runtime in case the FVP implements the legacy 245 * VE memory map. 246 */ 247 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 248 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 249 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 250 251 /* 252 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 253 * terminology. On a GICv2 system or mode, the lists will be merged and treated 254 * as Group 0 interrupts. 255 */ 256 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 257 ARM_G1S_IRQ_PROPS(grp), \ 258 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 259 GIC_INTR_CFG_LEVEL), \ 260 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 261 GIC_INTR_CFG_LEVEL) 262 263 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 264 265 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 266 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 267 268 #define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ 269 ARM_SP_IMAGE_NS_BUF_SIZE) 270 271 #endif /* PLATFORM_DEF_H */ 272