1 /* 2 * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 #endif 58 59 /* 60 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 61 * max size of BL32 image. 62 */ 63 #if defined(SPD_spmd) 64 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 65 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 66 #endif 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* No SCP in FVP */ 72 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 73 74 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 75 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 76 77 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 78 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 79 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 80 81 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 82 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 83 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 84 85 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 86 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 87 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 88 89 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 90 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 91 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 92 93 /* Range of kernel DTB load address */ 94 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 95 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 96 97 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 98 FVP_DTB_DRAM_MAP_START, \ 99 FVP_DTB_DRAM_MAP_SIZE, \ 100 MT_MEMORY | MT_RO | MT_NS) 101 102 /* 103 * On the FVP platform when using the EL3 SPMC implementation allocate the 104 * datastore for tracking shared memory descriptors in the TZC DRAM section 105 * to ensure sufficient storage can be allocated. 106 * Provide an implementation of the accessor method to allow the datastore 107 * details to be retrieved by the SPMC. 108 * The SPMC will take care of initializing the memory region. 109 */ 110 111 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 112 113 /* Define memory configuration for device tree files. */ 114 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 115 116 #if SPMC_AT_EL3 117 /* 118 * Number of Secure Partitions supported. 119 * SPMC at EL3, uses this count to configure the maximum number of supported 120 * secure partitions. 121 */ 122 #define SECURE_PARTITION_COUNT 1 123 124 /* 125 * Number of Normal World Partitions supported. 126 * SPMC at EL3, uses this count to configure the maximum number of supported 127 * NWd partitions. 128 */ 129 #define NS_PARTITION_COUNT 1 130 131 /* 132 * Number of Logical Partitions supported. 133 * SPMC at EL3, uses this count to configure the maximum number of supported 134 * logical partitions. 135 */ 136 #define MAX_EL3_LP_DESCS_COUNT 1 137 138 #endif /* SPMC_AT_EL3 */ 139 140 /* 141 * Load address of BL33 for this platform port 142 */ 143 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 144 145 #if TRANSFER_LIST 146 #define FW_HANDOFF_SIZE 0x4000 147 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - FW_HANDOFF_SIZE) 148 #endif 149 150 /* 151 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 152 * plat_arm_mmap array defined for each BL stage. 153 */ 154 #if defined(IMAGE_BL31) 155 # if SPM_MM 156 # define PLAT_ARM_MMAP_ENTRIES 10 157 # define MAX_XLAT_TABLES 9 158 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 159 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 160 # elif SPMC_AT_EL3 161 # define PLAT_ARM_MMAP_ENTRIES 13 162 # define MAX_XLAT_TABLES 11 163 # else 164 # define PLAT_ARM_MMAP_ENTRIES 9 165 # if USE_DEBUGFS 166 # if ENABLE_RME 167 # define MAX_XLAT_TABLES 9 168 # else 169 # define MAX_XLAT_TABLES 8 170 # endif 171 # else 172 # if ENABLE_RME 173 # define MAX_XLAT_TABLES 8 174 # elif DRTM_SUPPORT 175 # define MAX_XLAT_TABLES 8 176 # else 177 # define MAX_XLAT_TABLES 7 178 # endif 179 # endif 180 # endif 181 #elif defined(IMAGE_BL32) 182 # if SPMC_AT_EL3 183 # define PLAT_ARM_MMAP_ENTRIES 270 184 # define MAX_XLAT_TABLES 10 185 # else 186 # define PLAT_ARM_MMAP_ENTRIES 9 187 # define MAX_XLAT_TABLES 6 188 # endif 189 #elif !USE_ROMLIB 190 # if ENABLE_RME && defined(IMAGE_BL2) 191 # define PLAT_ARM_MMAP_ENTRIES 12 192 # define MAX_XLAT_TABLES 6 193 # else 194 # define PLAT_ARM_MMAP_ENTRIES 11 195 # define MAX_XLAT_TABLES 5 196 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 197 #else 198 # define PLAT_ARM_MMAP_ENTRIES 12 199 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 200 defined(IMAGE_BL2) && MEASURED_BOOT 201 # define MAX_XLAT_TABLES 7 202 # else 203 # define MAX_XLAT_TABLES 6 204 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 205 #endif 206 207 /* 208 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 209 * plus a little space for growth. 210 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 211 * area. 212 */ 213 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO 214 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 215 #else 216 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 217 #endif 218 219 /* 220 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 221 */ 222 223 #if USE_ROMLIB 224 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 225 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 226 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 227 #else 228 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 229 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 230 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 231 #endif 232 233 /* 234 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 235 * Maximum size of BL2 increases as Trusted SRAM size increases. 236 */ 237 #if CRYPTO_SUPPORT 238 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 239 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 240 (2 * PAGE_SIZE) - \ 241 FVP_BL2_ROMLIB_OPTIMIZATION) 242 #else 243 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 244 (3 * PAGE_SIZE) - \ 245 FVP_BL2_ROMLIB_OPTIMIZATION) 246 #endif 247 #elif ARM_BL31_IN_DRAM 248 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 249 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 250 #else 251 /** 252 * Default to just under half of SRAM to ensure there's enough room for really 253 * large BL31 build configurations when using the default SRAM size (256 Kb). 254 */ 255 #define PLAT_ARM_MAX_BL2_SIZE \ 256 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 257 FVP_BL2_ROMLIB_OPTIMIZATION) 258 #endif 259 260 #if RESET_TO_BL31 261 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 262 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 263 ARM_SHARED_RAM_SIZE - \ 264 ARM_L0_GPT_SIZE) 265 #else 266 /* 267 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 268 * calculated using the current BL31 PROGBITS debug size plus the sizes of 269 * BL2 and BL1-RW. 270 * Size of the BL31 PROGBITS increases as the SRAM size increases. 271 */ 272 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 273 ARM_SHARED_RAM_SIZE - \ 274 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 275 #endif /* RESET_TO_BL31 */ 276 277 #ifndef __aarch64__ 278 #if RESET_TO_SP_MIN 279 /* Size of Trusted SRAM - the first 4KB of shared memory */ 280 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 281 ARM_SHARED_RAM_SIZE) 282 #else 283 /* 284 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 285 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 286 * BL2 and BL1-RW 287 */ 288 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 289 #endif /* RESET_TO_SP_MIN */ 290 #endif 291 292 /* 293 * Size of cacheable stacks 294 */ 295 #if defined(IMAGE_BL1) 296 # if CRYPTO_SUPPORT 297 # define PLATFORM_STACK_SIZE UL(0x1000) 298 # else 299 # define PLATFORM_STACK_SIZE UL(0x500) 300 # endif /* CRYPTO_SUPPORT */ 301 #elif defined(IMAGE_BL2) 302 # if CRYPTO_SUPPORT 303 # define PLATFORM_STACK_SIZE UL(0x1000) 304 # else 305 # define PLATFORM_STACK_SIZE UL(0x600) 306 # endif /* CRYPTO_SUPPORT */ 307 #elif defined(IMAGE_BL2U) 308 # define PLATFORM_STACK_SIZE UL(0x400) 309 #elif defined(IMAGE_BL31) 310 # if DRTM_SUPPORT 311 # define PLATFORM_STACK_SIZE UL(0x1000) 312 # else 313 # define PLATFORM_STACK_SIZE UL(0x800) 314 # endif /* DRTM_SUPPORT */ 315 #elif defined(IMAGE_BL32) 316 # if SPMC_AT_EL3 317 # define PLATFORM_STACK_SIZE UL(0x1000) 318 # else 319 # define PLATFORM_STACK_SIZE UL(0x440) 320 # endif /* SPMC_AT_EL3 */ 321 #elif defined(IMAGE_RMM) 322 # define PLATFORM_STACK_SIZE UL(0x440) 323 #endif 324 325 #define MAX_IO_DEVICES 3 326 #define MAX_IO_HANDLES 4 327 328 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 329 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 330 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 331 332 #if ARM_GPT_SUPPORT 333 /* 334 * Offset of the FIP in the GPT image. BL1 component uses this option 335 * as it does not load the partition table to get the FIP base 336 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 337 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 338 */ 339 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 340 #endif /* ARM_GPT_SUPPORT */ 341 342 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 343 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 344 345 /* 346 * PL011 related constants 347 */ 348 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 349 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 350 351 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 352 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 353 354 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 355 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 356 357 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 358 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 359 360 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 361 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 362 363 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 364 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 365 366 /* CCI related constants */ 367 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 368 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 369 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 370 371 /* CCI-500/CCI-550 on Base platform */ 372 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 373 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 374 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 375 376 /* CCN related constants. Only CCN 502 is currently supported */ 377 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 378 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 379 380 /* System timer related constants */ 381 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 382 383 /* Mailbox base address */ 384 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 385 386 387 /* TrustZone controller related constants 388 * 389 * Currently only filters 0 and 2 are connected on Base FVP. 390 * Filter 0 : CPU clusters (no access to DRAM by default) 391 * Filter 1 : not connected 392 * Filter 2 : LCDs (access to VRAM allowed by default) 393 * Filter 3 : not connected 394 * Programming unconnected filters will have no effect at the 395 * moment. These filter could, however, be connected in future. 396 * So care should be taken not to configure the unused filters. 397 * 398 * Allow only non-secure access to all DRAM to supported devices. 399 * Give access to the CPUs and Virtio. Some devices 400 * would normally use the default ID so allow that too. 401 */ 402 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 403 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 404 405 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 406 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 407 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 408 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 409 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 410 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 411 412 /* 413 * GIC related constants to cater for both GICv2 and GICv3 instances of an 414 * FVP. They could be overridden at runtime in case the FVP implements the 415 * legacy VE memory map. 416 */ 417 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 418 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 419 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 420 421 /* 422 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 423 * terminology. On a GICv2 system or mode, the lists will be merged and treated 424 * as Group 0 interrupts. 425 */ 426 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 427 ARM_G1S_IRQ_PROPS(grp), \ 428 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 429 GIC_INTR_CFG_LEVEL), \ 430 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 431 GIC_INTR_CFG_LEVEL) 432 433 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 434 435 #if SDEI_IN_FCONF 436 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 437 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 438 #else 439 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 440 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 441 ARM_SDEI_PRIVATE_EVENTS, \ 442 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 443 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 444 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 445 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 446 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 447 #else 448 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 449 #endif 450 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 451 #endif 452 453 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 454 PLAT_SP_IMAGE_NS_BUF_SIZE) 455 456 #define PLAT_SP_PRI 0x20 457 458 /* 459 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 460 */ 461 #ifdef __aarch64__ 462 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 463 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 464 #else 465 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 466 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 467 #endif 468 469 /* 470 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 471 */ 472 #if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) 473 /* Account for additional measurements of secure partitions and SPM. */ 474 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 475 #else 476 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 477 #endif 478 479 /* 480 * Maximum size of Event Log buffer used for DRTM 481 */ 482 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 483 484 /* 485 * Number of MMAP entries used by DRTM implementation 486 */ 487 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 488 489 #endif /* PLATFORM_DEF_H */ 490