1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 /* Protected physical address size */ 59 #define PLAT_ARM_PPS (SZ_1T) 60 #endif /* ENABLE_RME */ 61 62 /* 63 * Max size of SPMC is 16MB for fvp. With SPMD enabled this value corresponds to 64 * max size of BL32 image. 65 */ 66 #if defined(SPD_spmd) 67 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 68 #define PLAT_ARM_SPMC_SIZE SZ_16M 69 #endif 70 71 /* Virtual address used by dynamic mem_protect for chunk_base */ 72 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 73 74 /* No SCP in FVP */ 75 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 76 77 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 78 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 79 80 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 81 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 82 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 83 84 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 85 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 86 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 87 88 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 89 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 90 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 91 92 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 93 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 94 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 95 96 /* 97 * On the FVP platform when using the EL3 SPMC implementation allocate the 98 * datastore for tracking shared memory descriptors in the TZC DRAM section 99 * to ensure sufficient storage can be allocated. 100 * Provide an implementation of the accessor method to allow the datastore 101 * details to be retrieved by the SPMC. 102 * The SPMC will take care of initializing the memory region. 103 */ 104 105 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 106 107 /* Define memory configuration for device tree files. */ 108 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 109 110 #if SPMC_AT_EL3 111 112 /* 113 * Number of Secure Partitions supported. 114 * SPMC at EL3, uses this count to configure the maximum number of supported 115 * secure partitions. 116 */ 117 #define SECURE_PARTITION_COUNT 1 118 119 /* 120 * Number of Normal World Partitions supported. 121 * SPMC at EL3, uses this count to configure the maximum number of supported 122 * NWd partitions. 123 */ 124 #define NS_PARTITION_COUNT 1 125 126 /* 127 * Number of Logical Partitions supported. 128 * SPMC at EL3, uses this count to configure the maximum number of supported 129 * logical partitions. 130 */ 131 #define MAX_EL3_LP_DESCS_COUNT 1 132 133 #endif /* SPMC_AT_EL3 */ 134 135 /* 136 * Load address of BL33 for this platform port 137 */ 138 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 139 140 #if TRANSFER_LIST 141 142 /* Define maximum size of sp manifest file. */ 143 #if defined(SPD_spmd) 144 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE SZ_4K 145 #else 146 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE UL(0x0) 147 #endif 148 149 /* 150 * PLAT_ARM_FW_HANDOFF_SIZE should be page-aligned to ensure proper xlat mapping. 151 * If it is not, generating the page table mapping for FW_HANDOFF will fail. 152 * Because PLAT_ARM_EVENT_LOG_MAX_SIZE is not guaranteed to be aligned, 153 * PLAT_ARM_FW_HANDOFF_SIZE must be explicitly aligned. 154 */ 155 #define PLAT_ARM_FW_HANDOFF_SIZE ((((PLAT_ARM_HW_CONFIG_SIZE + \ 156 PLAT_ARM_EVENT_LOG_MAX_SIZE + \ 157 PLAT_ARM_SPMC_SP_MANIFEST_SIZE) + \ 158 PAGE_SIZE_MASK) >> \ 159 PAGE_SIZE_SHIFT) << PAGE_SIZE_SHIFT) 160 161 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 162 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 163 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 164 165 #if RESET_TO_BL31 166 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 167 #endif 168 169 #else 170 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 171 #endif 172 173 /* 174 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 175 * plat_arm_mmap array defined for each BL stage. 176 */ 177 #if defined(IMAGE_BL31) 178 # if SPM_MM 179 # define PLAT_ARM_MMAP_ENTRIES 10 180 # define MAX_XLAT_TABLES 9 181 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 182 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 183 # elif SPMC_AT_EL3 184 # define PLAT_ARM_MMAP_ENTRIES 13 185 # define MAX_XLAT_TABLES 11 186 # define PLAT_SP_IMAGE_MMAP_REGIONS 31 187 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 13 188 # else 189 # define PLAT_ARM_MMAP_ENTRIES 9 190 # if USE_DEBUGFS 191 # if ENABLE_RME 192 # define MAX_XLAT_TABLES 9 193 # else 194 # define MAX_XLAT_TABLES 8 195 # endif 196 # else 197 # if ENABLE_RME 198 # define MAX_XLAT_TABLES 8 199 # elif DRTM_SUPPORT 200 # define MAX_XLAT_TABLES 8 201 # else 202 # define MAX_XLAT_TABLES 7 203 # endif 204 # endif 205 # endif 206 #elif defined(IMAGE_BL32) 207 # if SPMC_AT_EL3 208 # define PLAT_ARM_MMAP_ENTRIES 270 209 # define MAX_XLAT_TABLES 10 210 # else 211 # define PLAT_ARM_MMAP_ENTRIES 9 212 # define MAX_XLAT_TABLES 6 213 # endif 214 #elif !USE_ROMLIB 215 # if defined(IMAGE_BL2) && (ENABLE_RME || SPMC_AT_EL3) 216 # define PLAT_ARM_MMAP_ENTRIES 12 217 # define MAX_XLAT_TABLES 6 218 # else 219 # define PLAT_ARM_MMAP_ENTRIES 12 220 # define MAX_XLAT_TABLES 5 221 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 222 #else 223 # define PLAT_ARM_MMAP_ENTRIES 12 224 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 225 defined(IMAGE_BL2) && MEASURED_BOOT 226 # define MAX_XLAT_TABLES 7 227 # else 228 # define MAX_XLAT_TABLES 6 229 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 230 #endif 231 232 /* 233 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 234 * plus a little space for growth. 235 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 236 * area. 237 */ 238 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 239 FVP_TRUSTED_SRAM_SIZE == 512 240 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 241 #else 242 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 243 #endif 244 245 /* 246 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 247 */ 248 249 #if USE_ROMLIB 250 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 251 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 252 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 253 #else 254 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 255 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 256 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 257 #endif 258 259 /* 260 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 261 * Maximum size of BL2 increases as Trusted SRAM size increases. 262 */ 263 #if CRYPTO_SUPPORT 264 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 265 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 266 (2 * PAGE_SIZE) - \ 267 FVP_BL2_ROMLIB_OPTIMIZATION) 268 #else 269 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 270 (3 * PAGE_SIZE) - \ 271 FVP_BL2_ROMLIB_OPTIMIZATION) 272 #endif 273 #elif ARM_BL31_IN_DRAM 274 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 275 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 276 #else 277 /** 278 * Default to just under half of SRAM to ensure there's enough room for really 279 * large BL31 build configurations when using the default SRAM size (256 Kb). 280 */ 281 #define PLAT_ARM_MAX_BL2_SIZE \ 282 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 283 FVP_BL2_ROMLIB_OPTIMIZATION) 284 #endif 285 286 #if RESET_TO_BL31 287 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 288 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 289 ARM_SHARED_RAM_SIZE - \ 290 ARM_L0_GPT_SIZE) 291 #else 292 /* 293 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 294 * calculated using the current BL31 PROGBITS debug size plus the sizes of 295 * BL2 and BL1-RW. 296 * Size of the BL31 PROGBITS increases as the SRAM size increases. 297 */ 298 #if TRANSFER_LIST 299 #define PLAT_ARM_MAX_BL31_SIZE \ 300 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 301 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 302 #else 303 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 304 ARM_SHARED_RAM_SIZE - \ 305 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 306 #endif /* TRANSFER_LIST */ 307 #endif /* RESET_TO_BL31 */ 308 309 #ifndef __aarch64__ 310 #if RESET_TO_SP_MIN 311 /* Size of Trusted SRAM - the first 4KB of shared memory */ 312 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 313 ARM_SHARED_RAM_SIZE) 314 #else 315 /* 316 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 317 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 318 * BL2 and BL1-RW 319 */ 320 #if TRANSFER_LIST 321 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 322 ARM_SHARED_RAM_SIZE - \ 323 PLAT_ARM_FW_HANDOFF_SIZE) 324 #else 325 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 326 ARM_SHARED_RAM_SIZE - \ 327 ARM_FW_CONFIGS_SIZE) 328 #endif /* TRANSFER_LIST */ 329 #endif /* RESET_TO_SP_MIN */ 330 #endif 331 332 /* 333 * Size of cacheable stacks 334 */ 335 #if defined(IMAGE_BL1) 336 # if CRYPTO_SUPPORT 337 # define PLATFORM_STACK_SIZE UL(0x1000) 338 # else 339 # define PLATFORM_STACK_SIZE UL(0x500) 340 # endif /* CRYPTO_SUPPORT */ 341 #elif defined(IMAGE_BL2) 342 # if CRYPTO_SUPPORT 343 # define PLATFORM_STACK_SIZE UL(0x1000) 344 # else 345 # define PLATFORM_STACK_SIZE UL(0x600) 346 # endif /* CRYPTO_SUPPORT */ 347 #elif defined(IMAGE_BL2U) 348 # define PLATFORM_STACK_SIZE UL(0x400) 349 #elif defined(IMAGE_BL31) 350 # if DRTM_SUPPORT 351 # define PLATFORM_STACK_SIZE UL(0x1000) 352 # else 353 # define PLATFORM_STACK_SIZE UL(0x800) 354 # endif /* DRTM_SUPPORT */ 355 #elif defined(IMAGE_BL32) 356 # if SPMC_AT_EL3 357 # define PLATFORM_STACK_SIZE UL(0x1000) 358 # else 359 # define PLATFORM_STACK_SIZE UL(0x440) 360 # endif /* SPMC_AT_EL3 */ 361 #elif defined(IMAGE_RMM) 362 # define PLATFORM_STACK_SIZE UL(0x440) 363 #endif 364 365 #define MAX_IO_DEVICES 3 366 #define MAX_IO_HANDLES 4 367 368 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 369 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 370 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 371 372 #if ARM_GPT_SUPPORT 373 /* 374 * Offset of the FIP in the GPT image. BL1 component uses this option 375 * as it does not load the partition table to get the FIP base 376 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 377 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 378 */ 379 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 380 #endif /* ARM_GPT_SUPPORT */ 381 382 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 383 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 384 385 /* 386 * PL011 related constants 387 */ 388 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 389 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 390 391 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 392 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 393 394 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 395 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 396 397 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 398 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 399 400 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 401 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 402 403 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 404 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 405 406 /* CCI related constants */ 407 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 408 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 409 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 410 411 /* CCI-500/CCI-550 on Base platform */ 412 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 413 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 414 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 415 416 /* CCN related constants. Only CCN 502 is currently supported */ 417 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 418 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 419 420 /* System timer related constants */ 421 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 422 423 /* Mailbox base address */ 424 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 425 426 /* PCIe memory region 1 (Base Platform RevC only) */ 427 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 428 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 429 430 /* 431 * PCIe memory region 2 (Base Platform RevC only) 432 * The full size of the second PCI memory region is 256GB 433 * but for now we only allocate the L1 GPTs for the first 3GB. 434 */ 435 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 436 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 437 438 /* TrustZone controller related constants 439 * 440 * Currently only filters 0 and 2 are connected on Base FVP. 441 * Filter 0 : CPU clusters (no access to DRAM by default) 442 * Filter 1 : not connected 443 * Filter 2 : LCDs (access to VRAM allowed by default) 444 * Filter 3 : not connected 445 * Programming unconnected filters will have no effect at the 446 * moment. These filter could, however, be connected in future. 447 * So care should be taken not to configure the unused filters. 448 * 449 * Allow only non-secure access to all DRAM to supported devices. 450 * Give access to the CPUs and Virtio. Some devices 451 * would normally use the default ID so allow that too. 452 */ 453 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 454 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 455 456 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 457 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 458 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 459 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 460 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 461 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 462 463 /* 464 * GIC related constants to cater for both GICv2 and GICv3 instances of an 465 * FVP. They could be overridden at runtime in case the FVP implements the 466 * legacy VE memory map. 467 */ 468 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 469 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 470 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 471 472 /* 473 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 474 * terminology. On a GICv2 system or mode, the lists will be merged and treated 475 * as Group 0 interrupts. 476 */ 477 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 478 ARM_G1S_IRQ_PROPS(grp), \ 479 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 480 GIC_INTR_CFG_LEVEL), \ 481 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 482 GIC_INTR_CFG_LEVEL) 483 484 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 485 486 #if SDEI_IN_FCONF 487 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 488 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 489 #else 490 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 491 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 492 ARM_SDEI_PRIVATE_EVENTS, \ 493 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 494 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 495 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 496 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 497 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 498 #else 499 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 500 #endif 501 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 502 #endif 503 504 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 505 PLAT_SPM_BUF_SIZE) 506 507 #define PLAT_SP_PRI 0x20 508 509 /* 510 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 511 */ 512 #ifdef __aarch64__ 513 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 514 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 515 #else 516 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 517 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 518 #endif 519 520 /* 521 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 522 * TODO: calculate maximum EventLog size using the calculation: 523 * Maximum size of Event Log * Number of images 524 */ 525 #if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed))) 526 /* 527 * Account for additional measurements of secure partitions and SPM. 528 * Also, account for OP-TEE running with maximum number of SPs. 529 */ 530 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 531 #elif defined(IMAGE_BL1) && TRANSFER_LIST 532 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 533 #else 534 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 535 #endif 536 537 /* 538 * Maximum size of Event Log buffer used for DRTM 539 */ 540 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 541 542 /* 543 * Number of MMAP entries used by DRTM implementation 544 */ 545 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 546 547 #endif /* PLATFORM_DEF_H */ 548