1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <board_arm_def.h> 12 #include <common_def.h> 13 #include <tzc400.h> 14 #include <utils.h> 15 #include <v2m_def.h> 16 #include "../fvp_def.h" 17 18 /* Required platform porting definitions */ 19 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 20 PLATFORM_CORE_COUNT) 21 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 22 #define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER) 23 24 /* 25 * Other platform porting definitions are provided by included headers 26 */ 27 28 /* 29 * Required ARM standard platform porting definitions 30 */ 31 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 32 33 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 34 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 35 36 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 37 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 38 39 /* No SCP in FVP */ 40 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 41 42 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) 43 44 /* 45 * Load address of BL33 for this platform port 46 */ 47 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) 48 49 50 /* 51 * PL011 related constants 52 */ 53 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 54 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 55 56 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 57 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 58 59 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 60 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 61 62 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 63 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 64 65 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 66 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 67 68 /* CCI related constants */ 69 #define PLAT_ARM_CCI_BASE 0x2c090000 70 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 71 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 72 73 /* CCN related constants. Only CCN 502 is currently supported */ 74 #define PLAT_ARM_CCN_BASE 0x2e000000 75 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 76 77 /* System timer related constants */ 78 #define PLAT_ARM_NSTIMER_FRAME_ID 1 79 80 /* Mailbox base address */ 81 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 82 83 84 /* TrustZone controller related constants 85 * 86 * Currently only filters 0 and 2 are connected on Base FVP. 87 * Filter 0 : CPU clusters (no access to DRAM by default) 88 * Filter 1 : not connected 89 * Filter 2 : LCDs (access to VRAM allowed by default) 90 * Filter 3 : not connected 91 * Programming unconnected filters will have no effect at the 92 * moment. These filter could, however, be connected in future. 93 * So care should be taken not to configure the unused filters. 94 * 95 * Allow only non-secure access to all DRAM to supported devices. 96 * Give access to the CPUs and Virtio. Some devices 97 * would normally use the default ID so allow that too. 98 */ 99 #define PLAT_ARM_TZC_BASE 0x2a4a0000 100 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 101 102 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 103 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 104 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 105 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 106 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 107 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 108 109 /* 110 * GIC related constants to cater for both GICv2 and GICv3 instances of an 111 * FVP. They could be overriden at runtime in case the FVP implements the legacy 112 * VE memory map. 113 */ 114 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 115 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 116 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 117 118 /* 119 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 120 * terminology. On a GICv2 system or mode, the lists will be merged and treated 121 * as Group 0 interrupts. 122 */ 123 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 124 FVP_IRQ_TZ_WDOG, \ 125 FVP_IRQ_SEC_SYS_TIMER 126 127 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 128 129 #endif /* __PLATFORM_DEF_H__ */ 130