1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 #define PLAT_ARM_RMM_PAYLOAD_SIZE UL(0x800000) /* 2 * 4MB */ 59 60 /* Protected physical address size */ 61 #define PLAT_ARM_PPS (SZ_1T) 62 #endif /* ENABLE_RME */ 63 64 /* 65 * Max size of SPMC is 16MB for fvp. With SPMD enabled this value corresponds to 66 * max size of BL32 image. 67 */ 68 #if defined(SPD_spmd) 69 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 70 #define PLAT_ARM_SPMC_SIZE SZ_16M 71 #endif 72 73 /* Virtual address used by dynamic mem_protect for chunk_base */ 74 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 75 76 /* No SCP in FVP */ 77 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 78 79 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 80 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 81 82 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 83 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 84 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 85 86 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 87 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 88 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 89 90 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 91 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 92 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 93 94 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 95 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 96 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 97 98 /* 99 * On the FVP platform when using the EL3 SPMC implementation allocate the 100 * datastore for tracking shared memory descriptors in the TZC DRAM section 101 * to ensure sufficient storage can be allocated. 102 * Provide an implementation of the accessor method to allow the datastore 103 * details to be retrieved by the SPMC. 104 * The SPMC will take care of initializing the memory region. 105 */ 106 107 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 108 109 /* Define memory configuration for device tree files. */ 110 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 111 112 #if SPMC_AT_EL3 113 114 /* Define maximum size of sp manifest file. */ 115 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE U(0x1000) 116 117 /* 118 * Number of Secure Partitions supported. 119 * SPMC at EL3, uses this count to configure the maximum number of supported 120 * secure partitions. 121 */ 122 #define SECURE_PARTITION_COUNT 1 123 124 /* 125 * Number of Normal World Partitions supported. 126 * SPMC at EL3, uses this count to configure the maximum number of supported 127 * NWd partitions. 128 */ 129 #define NS_PARTITION_COUNT 1 130 131 /* 132 * Number of Logical Partitions supported. 133 * SPMC at EL3, uses this count to configure the maximum number of supported 134 * logical partitions. 135 */ 136 #define MAX_EL3_LP_DESCS_COUNT 1 137 138 #else /* !SPMC_AT_EL3 */ 139 140 /* Define maximum size of sp manifest file. */ 141 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE U(0x0) 142 143 #endif /* SPMC_AT_EL3 */ 144 145 /* 146 * Load address of BL33 for this platform port 147 */ 148 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 149 150 #if TRANSFER_LIST 151 #if SPMC_AT_EL3 152 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x6000) 153 #else 154 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000) 155 #endif 156 157 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 158 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 159 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 160 161 #if RESET_TO_BL31 162 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 163 #endif 164 165 #else 166 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 167 #endif 168 169 /* 170 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 171 * plat_arm_mmap array defined for each BL stage. 172 */ 173 #if defined(IMAGE_BL31) 174 # if SPM_MM 175 # define PLAT_ARM_MMAP_ENTRIES 10 176 # define MAX_XLAT_TABLES 9 177 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 178 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 179 # elif SPMC_AT_EL3 180 # define PLAT_ARM_MMAP_ENTRIES 13 181 # define MAX_XLAT_TABLES 11 182 # define PLAT_SP_IMAGE_MMAP_REGIONS 31 183 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 13 184 # else 185 # define PLAT_ARM_MMAP_ENTRIES 9 186 # if USE_DEBUGFS 187 # if ENABLE_RME 188 # define MAX_XLAT_TABLES 9 189 # else 190 # define MAX_XLAT_TABLES 8 191 # endif 192 # else 193 # if ENABLE_RME 194 # define MAX_XLAT_TABLES 8 195 # elif DRTM_SUPPORT 196 # define MAX_XLAT_TABLES 8 197 # else 198 # define MAX_XLAT_TABLES 7 199 # endif 200 # endif 201 # endif 202 #elif defined(IMAGE_BL32) 203 # if SPMC_AT_EL3 204 # define PLAT_ARM_MMAP_ENTRIES 270 205 # define MAX_XLAT_TABLES 10 206 # else 207 # define PLAT_ARM_MMAP_ENTRIES 9 208 # define MAX_XLAT_TABLES 6 209 # endif 210 #elif !USE_ROMLIB 211 # if defined(IMAGE_BL2) && (ENABLE_RME || SPMC_AT_EL3) 212 # define PLAT_ARM_MMAP_ENTRIES 12 213 # define MAX_XLAT_TABLES 6 214 # else 215 # define PLAT_ARM_MMAP_ENTRIES 12 216 # define MAX_XLAT_TABLES 5 217 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 218 #else 219 # define PLAT_ARM_MMAP_ENTRIES 12 220 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 221 defined(IMAGE_BL2) && MEASURED_BOOT 222 # define MAX_XLAT_TABLES 7 223 # else 224 # define MAX_XLAT_TABLES 6 225 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 226 #endif 227 228 /* 229 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 230 * plus a little space for growth. 231 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 232 * area. 233 */ 234 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 235 FVP_TRUSTED_SRAM_SIZE == 512 236 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 237 #else 238 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 239 #endif 240 241 /* 242 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 243 */ 244 245 #if USE_ROMLIB 246 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 247 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 248 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 249 #else 250 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 251 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 252 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 253 #endif 254 255 /* 256 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 257 * Maximum size of BL2 increases as Trusted SRAM size increases. 258 */ 259 #if CRYPTO_SUPPORT 260 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 261 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 262 (2 * PAGE_SIZE) - \ 263 FVP_BL2_ROMLIB_OPTIMIZATION) 264 #else 265 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 266 (3 * PAGE_SIZE) - \ 267 FVP_BL2_ROMLIB_OPTIMIZATION) 268 #endif 269 #elif ARM_BL31_IN_DRAM 270 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 271 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 272 #else 273 /** 274 * Default to just under half of SRAM to ensure there's enough room for really 275 * large BL31 build configurations when using the default SRAM size (256 Kb). 276 */ 277 #define PLAT_ARM_MAX_BL2_SIZE \ 278 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 279 FVP_BL2_ROMLIB_OPTIMIZATION) 280 #endif 281 282 #if RESET_TO_BL31 283 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 284 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 285 ARM_SHARED_RAM_SIZE - \ 286 ARM_L0_GPT_SIZE) 287 #else 288 /* 289 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 290 * calculated using the current BL31 PROGBITS debug size plus the sizes of 291 * BL2 and BL1-RW. 292 * Size of the BL31 PROGBITS increases as the SRAM size increases. 293 */ 294 #if TRANSFER_LIST 295 #define PLAT_ARM_MAX_BL31_SIZE \ 296 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 297 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 298 #else 299 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 300 ARM_SHARED_RAM_SIZE - \ 301 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 302 #endif /* TRANSFER_LIST */ 303 #endif /* RESET_TO_BL31 */ 304 305 #ifndef __aarch64__ 306 #if RESET_TO_SP_MIN 307 /* Size of Trusted SRAM - the first 4KB of shared memory */ 308 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 309 ARM_SHARED_RAM_SIZE) 310 #else 311 /* 312 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 313 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 314 * BL2 and BL1-RW 315 */ 316 #if TRANSFER_LIST 317 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 318 ARM_SHARED_RAM_SIZE - \ 319 PLAT_ARM_FW_HANDOFF_SIZE) 320 #else 321 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 322 ARM_SHARED_RAM_SIZE - \ 323 ARM_FW_CONFIGS_SIZE) 324 #endif /* TRANSFER_LIST */ 325 #endif /* RESET_TO_SP_MIN */ 326 #endif 327 328 /* 329 * Size of cacheable stacks 330 */ 331 #if defined(IMAGE_BL1) 332 # if CRYPTO_SUPPORT 333 # define PLATFORM_STACK_SIZE UL(0x1000) 334 # else 335 # define PLATFORM_STACK_SIZE UL(0x500) 336 # endif /* CRYPTO_SUPPORT */ 337 #elif defined(IMAGE_BL2) 338 # if CRYPTO_SUPPORT 339 # define PLATFORM_STACK_SIZE UL(0x1000) 340 # else 341 # define PLATFORM_STACK_SIZE UL(0x600) 342 # endif /* CRYPTO_SUPPORT */ 343 #elif defined(IMAGE_BL2U) 344 # define PLATFORM_STACK_SIZE UL(0x400) 345 #elif defined(IMAGE_BL31) 346 # if DRTM_SUPPORT 347 # define PLATFORM_STACK_SIZE UL(0x1000) 348 # else 349 # define PLATFORM_STACK_SIZE UL(0x800) 350 # endif /* DRTM_SUPPORT */ 351 #elif defined(IMAGE_BL32) 352 # if SPMC_AT_EL3 353 # define PLATFORM_STACK_SIZE UL(0x1000) 354 # else 355 # define PLATFORM_STACK_SIZE UL(0x440) 356 # endif /* SPMC_AT_EL3 */ 357 #elif defined(IMAGE_RMM) 358 # define PLATFORM_STACK_SIZE UL(0x440) 359 #endif 360 361 #define MAX_IO_DEVICES 3 362 #define MAX_IO_HANDLES 4 363 364 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 365 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 366 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 367 368 #if ARM_GPT_SUPPORT 369 /* 370 * Offset of the FIP in the GPT image. BL1 component uses this option 371 * as it does not load the partition table to get the FIP base 372 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 373 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 374 */ 375 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 376 #endif /* ARM_GPT_SUPPORT */ 377 378 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 379 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 380 381 /* 382 * PL011 related constants 383 */ 384 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 385 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 386 387 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 388 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 389 390 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 391 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 392 393 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 394 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 395 396 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 397 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 398 399 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 400 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 401 402 /* CCI related constants */ 403 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 404 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 405 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 406 407 /* CCI-500/CCI-550 on Base platform */ 408 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 409 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 410 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 411 412 /* CCN related constants. Only CCN 502 is currently supported */ 413 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 414 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 415 416 /* System timer related constants */ 417 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 418 419 /* Mailbox base address */ 420 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 421 422 /* PCIe memory region 1 (Base Platform RevC only) */ 423 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 424 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 425 426 /* 427 * PCIe memory region 2 (Base Platform RevC only) 428 * The full size of the second PCI memory region is 256GB 429 * but for now we only allocate the L1 GPTs for the first 3GB. 430 */ 431 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 432 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 433 434 /* TrustZone controller related constants 435 * 436 * Currently only filters 0 and 2 are connected on Base FVP. 437 * Filter 0 : CPU clusters (no access to DRAM by default) 438 * Filter 1 : not connected 439 * Filter 2 : LCDs (access to VRAM allowed by default) 440 * Filter 3 : not connected 441 * Programming unconnected filters will have no effect at the 442 * moment. These filter could, however, be connected in future. 443 * So care should be taken not to configure the unused filters. 444 * 445 * Allow only non-secure access to all DRAM to supported devices. 446 * Give access to the CPUs and Virtio. Some devices 447 * would normally use the default ID so allow that too. 448 */ 449 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 450 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 451 452 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 453 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 454 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 455 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 456 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 457 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 458 459 /* 460 * GIC related constants to cater for both GICv2 and GICv3 instances of an 461 * FVP. They could be overridden at runtime in case the FVP implements the 462 * legacy VE memory map. 463 */ 464 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 465 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 466 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 467 468 /* 469 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 470 * terminology. On a GICv2 system or mode, the lists will be merged and treated 471 * as Group 0 interrupts. 472 */ 473 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 474 ARM_G1S_IRQ_PROPS(grp), \ 475 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 476 GIC_INTR_CFG_LEVEL), \ 477 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 478 GIC_INTR_CFG_LEVEL) 479 480 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 481 482 #if SDEI_IN_FCONF 483 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 484 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 485 #else 486 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 487 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 488 ARM_SDEI_PRIVATE_EVENTS, \ 489 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 490 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 491 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 492 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 493 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 494 #else 495 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 496 #endif 497 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 498 #endif 499 500 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 501 PLAT_SPM_BUF_SIZE) 502 503 #define PLAT_SP_PRI 0x20 504 505 /* 506 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 507 */ 508 #ifdef __aarch64__ 509 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 510 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 511 #else 512 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 513 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 514 #endif 515 516 /* 517 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 518 * TODO: calculate maximum EventLog size using the calculation: 519 * Maximum size of Event Log * Number of images 520 */ 521 #if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed))) 522 /* 523 * Account for additional measurements of secure partitions and SPM. 524 * Also, account for OP-TEE running with maximum number of SPs. 525 */ 526 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 527 #elif defined(IMAGE_BL1) && TRANSFER_LIST 528 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 529 #else 530 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 531 #endif 532 533 /* 534 * Maximum size of Event Log buffer used for DRTM 535 */ 536 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 537 538 /* 539 * Number of MMAP entries used by DRTM implementation 540 */ 541 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 542 543 #endif /* PLATFORM_DEF_H */ 544