1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT \ 21 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 22 23 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 24 PLATFORM_CORE_COUNT) + 1 25 26 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 27 28 /* 29 * Other platform porting definitions are provided by included headers 30 */ 31 32 /* 33 * Required ARM standard platform porting definitions 34 */ 35 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 36 37 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 38 39 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 40 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 41 42 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 43 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 44 45 /* virtual address used by dynamic mem_protect for chunk_base */ 46 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 47 48 /* No SCP in FVP */ 49 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 50 51 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 52 53 /* 54 * Load address of BL33 for this platform port 55 */ 56 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 57 58 /* 59 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 60 * plat_arm_mmap array defined for each BL stage. 61 */ 62 #if defined(IMAGE_BL31) 63 # if ENABLE_SPM 64 # define PLAT_ARM_MMAP_ENTRIES 9 65 # define MAX_XLAT_TABLES 9 66 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 67 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 68 # else 69 # define PLAT_ARM_MMAP_ENTRIES 8 70 # define MAX_XLAT_TABLES 5 71 # endif 72 #elif defined(IMAGE_BL32) 73 # define PLAT_ARM_MMAP_ENTRIES 8 74 # define MAX_XLAT_TABLES 5 75 #elif !USE_ROMLIB 76 # define PLAT_ARM_MMAP_ENTRIES 11 77 # define MAX_XLAT_TABLES 5 78 #else 79 # define PLAT_ARM_MMAP_ENTRIES 12 80 # define MAX_XLAT_TABLES 6 81 #endif 82 83 /* 84 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 85 * plus a little space for growth. 86 */ 87 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 88 89 /* 90 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 91 */ 92 93 #if USE_ROMLIB 94 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 95 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 96 #else 97 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 98 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 99 #endif 100 101 /* 102 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 103 * little space for growth. 104 */ 105 #if TRUSTED_BOARD_BOOT 106 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 107 #else 108 # define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) 109 #endif 110 111 /* 112 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 113 * calculated using the current BL31 PROGBITS debug size plus the sizes of 114 * BL2 and BL1-RW 115 */ 116 #if ENABLE_SPM && !SPM_MM 117 #define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) 118 #else 119 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 120 #endif 121 122 #ifdef AARCH32 123 /* 124 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 125 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 126 * BL2 and BL1-RW 127 */ 128 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 129 #endif 130 131 /* 132 * Size of cacheable stacks 133 */ 134 #if defined(IMAGE_BL1) 135 # if TRUSTED_BOARD_BOOT 136 # define PLATFORM_STACK_SIZE UL(0x1000) 137 # else 138 # define PLATFORM_STACK_SIZE UL(0x440) 139 # endif 140 #elif defined(IMAGE_BL2) 141 # if TRUSTED_BOARD_BOOT 142 # define PLATFORM_STACK_SIZE UL(0x1000) 143 # else 144 # define PLATFORM_STACK_SIZE UL(0x400) 145 # endif 146 #elif defined(IMAGE_BL2U) 147 # define PLATFORM_STACK_SIZE UL(0x400) 148 #elif defined(IMAGE_BL31) 149 # if ENABLE_SPM 150 # define PLATFORM_STACK_SIZE UL(0x600) 151 # elif PLAT_XLAT_TABLES_DYNAMIC 152 # define PLATFORM_STACK_SIZE UL(0x800) 153 # else 154 # define PLATFORM_STACK_SIZE UL(0x400) 155 # endif 156 #elif defined(IMAGE_BL32) 157 # define PLATFORM_STACK_SIZE UL(0x440) 158 #endif 159 160 #define MAX_IO_DEVICES 3 161 #define MAX_IO_HANDLES 4 162 163 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 164 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 165 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 166 167 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 168 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 169 170 /* 171 * PL011 related constants 172 */ 173 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 174 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 175 176 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 177 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 178 179 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 180 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 181 182 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 183 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 184 185 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 186 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 187 188 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 189 190 /* CCI related constants */ 191 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 192 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 193 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 194 195 /* CCI-500/CCI-550 on Base platform */ 196 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 197 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 198 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 199 200 /* CCN related constants. Only CCN 502 is currently supported */ 201 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 202 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 203 204 /* System timer related constants */ 205 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 206 207 /* Mailbox base address */ 208 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 209 210 211 /* TrustZone controller related constants 212 * 213 * Currently only filters 0 and 2 are connected on Base FVP. 214 * Filter 0 : CPU clusters (no access to DRAM by default) 215 * Filter 1 : not connected 216 * Filter 2 : LCDs (access to VRAM allowed by default) 217 * Filter 3 : not connected 218 * Programming unconnected filters will have no effect at the 219 * moment. These filter could, however, be connected in future. 220 * So care should be taken not to configure the unused filters. 221 * 222 * Allow only non-secure access to all DRAM to supported devices. 223 * Give access to the CPUs and Virtio. Some devices 224 * would normally use the default ID so allow that too. 225 */ 226 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 227 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 228 229 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 230 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 231 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 232 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 233 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 234 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 235 236 /* 237 * GIC related constants to cater for both GICv2 and GICv3 instances of an 238 * FVP. They could be overriden at runtime in case the FVP implements the legacy 239 * VE memory map. 240 */ 241 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 242 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 243 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 244 245 /* 246 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 247 * terminology. On a GICv2 system or mode, the lists will be merged and treated 248 * as Group 0 interrupts. 249 */ 250 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 251 ARM_G1S_IRQ_PROPS(grp), \ 252 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 253 GIC_INTR_CFG_LEVEL), \ 254 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 255 GIC_INTR_CFG_LEVEL) 256 257 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 258 259 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 260 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 261 262 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 263 PLAT_SP_IMAGE_NS_BUF_SIZE) 264 265 #define PLAT_SP_PRI PLAT_RAS_PRI 266 267 #endif /* PLATFORM_DEF_H */ 268