1 /* 2 * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 /* 34 * Other platform porting definitions are provided by included headers 35 */ 36 37 /* 38 * Required ARM standard platform porting definitions 39 */ 40 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 41 42 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 43 44 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 45 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 46 47 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 48 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 49 50 #if ENABLE_RME 51 #define PLAT_ARM_RMM_BASE (RMM_BASE) 52 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 53 #endif 54 55 /* 56 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 57 * max size of BL32 image. 58 */ 59 #if defined(SPD_spmd) 60 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 61 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 62 #endif 63 64 /* virtual address used by dynamic mem_protect for chunk_base */ 65 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 66 67 /* No SCP in FVP */ 68 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 69 70 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 71 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 72 73 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 74 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 75 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 76 77 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 78 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 79 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 80 81 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 82 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 83 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 84 85 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 86 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 87 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 88 89 /* Range of kernel DTB load address */ 90 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 91 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 92 93 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 94 FVP_DTB_DRAM_MAP_START, \ 95 FVP_DTB_DRAM_MAP_SIZE, \ 96 MT_MEMORY | MT_RO | MT_NS) 97 98 #if SPMC_AT_EL3 99 /* 100 * Number of Secure Partitions supported. 101 * SPMC at EL3, uses this count to configure the maximum number of supported 102 * secure partitions. 103 */ 104 #define SECURE_PARTITION_COUNT 1 105 106 /* 107 * Number of Normal World Partitions supported. 108 * SPMC at EL3, uses this count to configure the maximum number of supported 109 * NWd partitions. 110 */ 111 #define NS_PARTITION_COUNT 1 112 113 /* 114 * Number of Logical Partitions supported. 115 * SPMC at EL3, uses this count to configure the maximum number of supported 116 * logical partitions. 117 */ 118 #define MAX_EL3_LP_DESCS_COUNT 1 119 120 #endif /* SPMC_AT_EL3 */ 121 122 /* 123 * Load address of BL33 for this platform port 124 */ 125 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 126 127 /* 128 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 129 * plat_arm_mmap array defined for each BL stage. 130 */ 131 #if defined(IMAGE_BL31) 132 # if SPM_MM 133 # define PLAT_ARM_MMAP_ENTRIES 10 134 # define MAX_XLAT_TABLES 9 135 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 136 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 137 # elif SPMC_AT_EL3 138 # define PLAT_ARM_MMAP_ENTRIES 13 139 # define MAX_XLAT_TABLES 11 140 # else 141 # define PLAT_ARM_MMAP_ENTRIES 9 142 # if USE_DEBUGFS 143 # if ENABLE_RME 144 # define MAX_XLAT_TABLES 9 145 # else 146 # define MAX_XLAT_TABLES 8 147 # endif 148 # else 149 # if ENABLE_RME 150 # define MAX_XLAT_TABLES 8 151 # elif DRTM_SUPPORT 152 # define MAX_XLAT_TABLES 8 153 # else 154 # define MAX_XLAT_TABLES 7 155 # endif 156 # endif 157 # endif 158 #elif defined(IMAGE_BL32) 159 # if SPMC_AT_EL3 160 # define PLAT_ARM_MMAP_ENTRIES 270 161 # define MAX_XLAT_TABLES 10 162 # else 163 # define PLAT_ARM_MMAP_ENTRIES 9 164 # define MAX_XLAT_TABLES 6 165 # endif 166 #elif !USE_ROMLIB 167 # define PLAT_ARM_MMAP_ENTRIES 11 168 # define MAX_XLAT_TABLES 5 169 #else 170 # define PLAT_ARM_MMAP_ENTRIES 12 171 # define MAX_XLAT_TABLES 6 172 #endif 173 174 /* 175 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 176 * plus a little space for growth. 177 */ 178 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 179 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 180 #else 181 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 182 #endif 183 184 /* 185 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 186 */ 187 188 #if USE_ROMLIB 189 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 190 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 191 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 192 #else 193 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 194 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 195 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 196 #endif 197 198 /* 199 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 200 * little space for growth. 201 */ 202 #if CRYPTO_SUPPORT 203 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 204 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 205 #else 206 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 207 #endif 208 #elif ARM_BL31_IN_DRAM 209 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 210 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 211 #else 212 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 213 #endif 214 215 #if RESET_TO_BL31 216 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 217 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 218 ARM_SHARED_RAM_SIZE - \ 219 ARM_L0_GPT_SIZE) 220 #else 221 /* 222 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 223 * calculated using the current BL31 PROGBITS debug size plus the sizes of 224 * BL2 and BL1-RW 225 */ 226 #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) 227 #endif /* RESET_TO_BL31 */ 228 229 #ifndef __aarch64__ 230 #if RESET_TO_SP_MIN 231 /* Size of Trusted SRAM - the first 4KB of shared memory */ 232 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 233 ARM_SHARED_RAM_SIZE) 234 #else 235 /* 236 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 237 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 238 * BL2 and BL1-RW 239 */ 240 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 241 #endif /* RESET_TO_SP_MIN */ 242 #endif 243 244 /* 245 * Size of cacheable stacks 246 */ 247 #if defined(IMAGE_BL1) 248 # if CRYPTO_SUPPORT 249 # define PLATFORM_STACK_SIZE UL(0x1000) 250 # else 251 # define PLATFORM_STACK_SIZE UL(0x500) 252 # endif /* CRYPTO_SUPPORT */ 253 #elif defined(IMAGE_BL2) 254 # if CRYPTO_SUPPORT 255 # define PLATFORM_STACK_SIZE UL(0x1000) 256 # else 257 # define PLATFORM_STACK_SIZE UL(0x600) 258 # endif /* CRYPTO_SUPPORT */ 259 #elif defined(IMAGE_BL2U) 260 # define PLATFORM_STACK_SIZE UL(0x400) 261 #elif defined(IMAGE_BL31) 262 # if DRTM_SUPPORT 263 # define PLATFORM_STACK_SIZE UL(0x1000) 264 # else 265 # define PLATFORM_STACK_SIZE UL(0x800) 266 # endif /* DRTM_SUPPORT */ 267 #elif defined(IMAGE_BL32) 268 # if SPMC_AT_EL3 269 # define PLATFORM_STACK_SIZE UL(0x1000) 270 # else 271 # define PLATFORM_STACK_SIZE UL(0x440) 272 # endif /* SPMC_AT_EL3 */ 273 #elif defined(IMAGE_RMM) 274 # define PLATFORM_STACK_SIZE UL(0x440) 275 #endif 276 277 #define MAX_IO_DEVICES 3 278 #define MAX_IO_HANDLES 4 279 280 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 281 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 282 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 283 284 #if ARM_GPT_SUPPORT 285 /* 286 * Offset of the FIP in the GPT image. BL1 component uses this option 287 * as it does not load the partition table to get the FIP base 288 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 289 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 290 */ 291 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 292 #endif /* ARM_GPT_SUPPORT */ 293 294 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 295 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 296 297 /* 298 * PL011 related constants 299 */ 300 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 301 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 302 303 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 304 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 305 306 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 307 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 308 309 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 310 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 311 312 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 313 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 314 315 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 316 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 317 318 /* CCI related constants */ 319 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 320 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 321 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 322 323 /* CCI-500/CCI-550 on Base platform */ 324 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 325 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 326 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 327 328 /* CCN related constants. Only CCN 502 is currently supported */ 329 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 330 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 331 332 /* System timer related constants */ 333 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 334 335 /* Mailbox base address */ 336 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 337 338 339 /* TrustZone controller related constants 340 * 341 * Currently only filters 0 and 2 are connected on Base FVP. 342 * Filter 0 : CPU clusters (no access to DRAM by default) 343 * Filter 1 : not connected 344 * Filter 2 : LCDs (access to VRAM allowed by default) 345 * Filter 3 : not connected 346 * Programming unconnected filters will have no effect at the 347 * moment. These filter could, however, be connected in future. 348 * So care should be taken not to configure the unused filters. 349 * 350 * Allow only non-secure access to all DRAM to supported devices. 351 * Give access to the CPUs and Virtio. Some devices 352 * would normally use the default ID so allow that too. 353 */ 354 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 355 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 356 357 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 358 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 359 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 360 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 361 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 362 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 363 364 /* 365 * GIC related constants to cater for both GICv2 and GICv3 instances of an 366 * FVP. They could be overridden at runtime in case the FVP implements the 367 * legacy VE memory map. 368 */ 369 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 370 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 371 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 372 373 /* 374 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 375 * terminology. On a GICv2 system or mode, the lists will be merged and treated 376 * as Group 0 interrupts. 377 */ 378 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 379 ARM_G1S_IRQ_PROPS(grp), \ 380 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 381 GIC_INTR_CFG_LEVEL), \ 382 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 383 GIC_INTR_CFG_LEVEL) 384 385 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 386 387 #if SDEI_IN_FCONF 388 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 389 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 390 #else 391 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 392 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 393 #endif 394 395 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 396 PLAT_SP_IMAGE_NS_BUF_SIZE) 397 398 #define PLAT_SP_PRI PLAT_RAS_PRI 399 400 /* 401 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 402 */ 403 #ifdef __aarch64__ 404 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 405 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 406 #else 407 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 408 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 409 #endif 410 411 /* 412 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 413 */ 414 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 415 416 /* 417 * Maximum size of Event Log buffer used for DRTM 418 */ 419 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 420 421 /* 422 * Number of MMAP entries used by DRTM implementation 423 */ 424 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 425 426 #endif /* PLATFORM_DEF_H */ 427