1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 #include <arm_def.h> 22 #include <arm_spm_def.h> 23 #include <board_arm_def.h> 24 #include <common_def.h> 25 #include <tzc400.h> 26 #include <utils_def.h> 27 #include <v2m_def.h> 28 #include "../fvp_def.h" 29 30 /* Required platform porting definitions */ 31 #define PLATFORM_CORE_COUNT \ 32 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 33 34 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 35 PLATFORM_CORE_COUNT) + 1 36 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 39 /* 40 * Other platform porting definitions are provided by included headers 41 */ 42 43 /* 44 * Required ARM standard platform porting definitions 45 */ 46 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 49 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 53 54 /* virtual address used by dynamic mem_protect for chunk_base */ 55 #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 56 57 /* No SCP in FVP */ 58 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 59 60 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 61 62 /* 63 * Load address of BL33 for this platform port 64 */ 65 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + U(0x8000000)) 66 67 /* 68 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 69 * plat_arm_mmap array defined for each BL stage. 70 */ 71 #if defined(IMAGE_BL31) 72 # if ENABLE_SPM 73 # define PLAT_ARM_MMAP_ENTRIES 9 74 # define MAX_XLAT_TABLES 7 75 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 76 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 77 # else 78 # define PLAT_ARM_MMAP_ENTRIES 8 79 # define MAX_XLAT_TABLES 5 80 # endif 81 #elif defined(IMAGE_BL32) 82 # define PLAT_ARM_MMAP_ENTRIES 8 83 # define MAX_XLAT_TABLES 5 84 #elif !USE_ROMLIB 85 # define PLAT_ARM_MMAP_ENTRIES 11 86 # define MAX_XLAT_TABLES 5 87 #else 88 # define PLAT_ARM_MMAP_ENTRIES 12 89 # define MAX_XLAT_TABLES 6 90 #endif 91 92 /* 93 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 94 * plus a little space for growth. 95 */ 96 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 97 98 /* 99 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 100 */ 101 102 #if USE_ROMLIB 103 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 104 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 105 #else 106 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 107 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 108 #endif 109 110 /* 111 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 112 * little space for growth. 113 */ 114 #if TRUSTED_BOARD_BOOT 115 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 116 #else 117 # define PLAT_ARM_MAX_BL2_SIZE 0x11000 118 #endif 119 120 /* 121 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 122 * calculated using the current BL31 PROGBITS debug size plus the sizes of 123 * BL2 and BL1-RW 124 */ 125 #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 126 127 #ifdef AARCH32 128 /* 129 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 130 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 131 * BL2 and BL1-RW 132 */ 133 # define PLAT_ARM_MAX_BL32_SIZE 0x3B000 134 #endif 135 136 /* 137 * PL011 related constants 138 */ 139 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 140 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 141 142 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 143 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 144 145 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 146 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 147 148 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 149 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 150 151 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 152 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 153 154 #define PLAT_FVP_SMMUV3_BASE 0x2b400000 155 156 /* CCI related constants */ 157 #define PLAT_FVP_CCI400_BASE 0x2c090000 158 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 159 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 160 161 /* CCI-500/CCI-550 on Base platform */ 162 #define PLAT_FVP_CCI5XX_BASE 0x2a000000 163 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 164 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 165 166 /* CCN related constants. Only CCN 502 is currently supported */ 167 #define PLAT_ARM_CCN_BASE 0x2e000000 168 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 169 170 /* System timer related constants */ 171 #define PLAT_ARM_NSTIMER_FRAME_ID 1 172 173 /* Mailbox base address */ 174 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 175 176 177 /* TrustZone controller related constants 178 * 179 * Currently only filters 0 and 2 are connected on Base FVP. 180 * Filter 0 : CPU clusters (no access to DRAM by default) 181 * Filter 1 : not connected 182 * Filter 2 : LCDs (access to VRAM allowed by default) 183 * Filter 3 : not connected 184 * Programming unconnected filters will have no effect at the 185 * moment. These filter could, however, be connected in future. 186 * So care should be taken not to configure the unused filters. 187 * 188 * Allow only non-secure access to all DRAM to supported devices. 189 * Give access to the CPUs and Virtio. Some devices 190 * would normally use the default ID so allow that too. 191 */ 192 #define PLAT_ARM_TZC_BASE 0x2a4a0000 193 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 194 195 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 196 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 197 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 198 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 199 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 200 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 201 202 /* 203 * GIC related constants to cater for both GICv2 and GICv3 instances of an 204 * FVP. They could be overriden at runtime in case the FVP implements the legacy 205 * VE memory map. 206 */ 207 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 208 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 209 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 210 211 /* 212 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 213 * terminology. On a GICv2 system or mode, the lists will be merged and treated 214 * as Group 0 interrupts. 215 */ 216 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 217 ARM_G1S_IRQ_PROPS(grp), \ 218 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 219 GIC_INTR_CFG_LEVEL), \ 220 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 221 GIC_INTR_CFG_LEVEL) 222 223 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 224 225 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 226 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 227 228 #define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ 229 ARM_SP_IMAGE_NS_BUF_SIZE) 230 231 #endif /* __PLATFORM_DEF_H__ */ 232