1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <arm_spm_def.h> 12 #include <board_arm_def.h> 13 #include <common_def.h> 14 #include <tzc400.h> 15 #include <utils_def.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT \ 21 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 22 23 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 24 PLATFORM_CORE_COUNT) + 1 25 26 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 27 28 /* 29 * Other platform porting definitions are provided by included headers 30 */ 31 32 /* 33 * Required ARM standard platform porting definitions 34 */ 35 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 36 37 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 38 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 39 40 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 41 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 42 43 /* No SCP in FVP */ 44 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 45 46 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 47 48 /* 49 * Load address of BL33 for this platform port 50 */ 51 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) 52 53 54 /* 55 * PL011 related constants 56 */ 57 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 58 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 59 60 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 61 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 62 63 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 64 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 65 66 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 67 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 68 69 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 70 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 71 72 #define PLAT_FVP_SMMUV3_BASE 0x2b400000 73 74 /* CCI related constants */ 75 #define PLAT_FVP_CCI400_BASE 0x2c090000 76 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 77 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 78 79 /* CCI-500/CCI-550 on Base platform */ 80 #define PLAT_FVP_CCI5XX_BASE 0x2a000000 81 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 82 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 83 84 /* CCN related constants. Only CCN 502 is currently supported */ 85 #define PLAT_ARM_CCN_BASE 0x2e000000 86 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 87 88 /* System timer related constants */ 89 #define PLAT_ARM_NSTIMER_FRAME_ID 1 90 91 /* Mailbox base address */ 92 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 93 94 95 /* TrustZone controller related constants 96 * 97 * Currently only filters 0 and 2 are connected on Base FVP. 98 * Filter 0 : CPU clusters (no access to DRAM by default) 99 * Filter 1 : not connected 100 * Filter 2 : LCDs (access to VRAM allowed by default) 101 * Filter 3 : not connected 102 * Programming unconnected filters will have no effect at the 103 * moment. These filter could, however, be connected in future. 104 * So care should be taken not to configure the unused filters. 105 * 106 * Allow only non-secure access to all DRAM to supported devices. 107 * Give access to the CPUs and Virtio. Some devices 108 * would normally use the default ID so allow that too. 109 */ 110 #define PLAT_ARM_TZC_BASE 0x2a4a0000 111 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 112 113 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 114 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 115 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 116 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 117 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 118 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 119 120 /* 121 * GIC related constants to cater for both GICv2 and GICv3 instances of an 122 * FVP. They could be overriden at runtime in case the FVP implements the legacy 123 * VE memory map. 124 */ 125 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 126 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 127 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 128 129 /* 130 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 131 * terminology. On a GICv2 system or mode, the lists will be merged and treated 132 * as Group 0 interrupts. 133 */ 134 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 135 FVP_IRQ_TZ_WDOG, \ 136 FVP_IRQ_SEC_SYS_TIMER 137 138 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 139 140 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 141 ARM_G1S_IRQ_PROPS(grp), \ 142 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_LEVEL), \ 144 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_LEVEL) 146 147 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 148 149 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 150 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 151 152 #endif /* __PLATFORM_DEF_H__ */ 153