1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <drivers/arm/smmu_v3.h> 10 #include <lib/fconf/fconf.h> 11 #include <plat/arm/common/arm_config.h> 12 #include <plat/arm/common/plat_arm.h> 13 #include <plat/common/platform.h> 14 15 #include "fvp_private.h" 16 17 uintptr_t hw_config_dtb; 18 19 void __init bl31_early_platform_setup2(u_register_t arg0, 20 u_register_t arg1, u_register_t arg2, u_register_t arg3) 21 { 22 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 23 24 /* Initialize the platform config for future decision making */ 25 fvp_config_setup(); 26 27 /* 28 * Initialize the correct interconnect for this cluster during cold 29 * boot. No need for locks as no other CPU is active. 30 */ 31 fvp_interconnect_init(); 32 33 /* 34 * Enable coherency in interconnect for the primary CPU's cluster. 35 * Earlier bootloader stages might already do this (e.g. Trusted 36 * Firmware's BL1 does it) but we can't assume so. There is no harm in 37 * executing this code twice anyway. 38 * FVP PSCI code will enable coherency for other clusters. 39 */ 40 fvp_interconnect_enable(); 41 42 /* Initialize System level generic or SP804 timer */ 43 fvp_timer_init(); 44 45 /* On FVP RevC, initialize SMMUv3 */ 46 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) 47 smmuv3_init(PLAT_FVP_SMMUV3_BASE); 48 49 hw_config_dtb = arg2; 50 } 51 52 void __init bl31_plat_arch_setup(void) 53 { 54 arm_bl31_plat_arch_setup(); 55 56 /* 57 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run. 58 * So there is no BL2 to load the HW_CONFIG dtb into memory before 59 * control is passed to BL31. 60 */ 61 #if !RESET_TO_BL31 && !BL2_AT_EL3 62 assert(hw_config_dtb != 0U); 63 64 INFO("BL31 FCONF: HW_CONFIG address = %p\n", (void *)hw_config_dtb); 65 fconf_populate("HW_CONFIG", hw_config_dtb); 66 #endif 67 } 68