1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <common/interrupt_props.h> 10 #include <drivers/arm/gicv2.h> 11 #include <lib/mmio.h> 12 #include <lib/xlat_tables/xlat_mmu_helpers.h> 13 #include <plat/common/platform.h> 14 #include <platform_def.h> 15 16 #include "aml_private.h" 17 18 /* 19 * Placeholder variables for copying the arguments that have been passed to 20 * BL31 from BL2. 21 */ 22 static entry_point_info_t bl33_image_ep_info; 23 static image_info_t bl30_image_info; 24 static image_info_t bl301_image_info; 25 26 /******************************************************************************* 27 * Return a pointer to the 'entry_point_info' structure of the next image for 28 * the security state specified. BL33 corresponds to the non-secure image type 29 * while BL32 corresponds to the secure image type. A NULL pointer is returned 30 * if the image does not exist. 31 ******************************************************************************/ 32 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 33 { 34 entry_point_info_t *next_image_info; 35 36 assert(type == NON_SECURE); 37 38 next_image_info = &bl33_image_ep_info; 39 40 /* None of the images can have 0x0 as the entrypoint. */ 41 if (next_image_info->pc != 0U) { 42 return next_image_info; 43 } else { 44 return NULL; 45 } 46 } 47 48 /******************************************************************************* 49 * Perform any BL31 early platform setup. Here is an opportunity to copy 50 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before 51 * they are lost (potentially). This needs to be done before the MMU is 52 * initialized so that the memory layout can be used while creating page 53 * tables. BL2 has flushed this information to memory, so we are guaranteed 54 * to pick up good data. 55 ******************************************************************************/ 56 struct gxl_bl31_param { 57 param_header_t h; 58 image_info_t *bl31_image_info; 59 entry_point_info_t *bl32_ep_info; 60 image_info_t *bl32_image_info; 61 entry_point_info_t *bl33_ep_info; 62 image_info_t *bl33_image_info; 63 image_info_t *scp_image_info[]; 64 }; 65 66 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 67 u_register_t arg2, u_register_t arg3) 68 { 69 struct gxl_bl31_param *from_bl2; 70 71 /* Initialize the console to provide early debug support */ 72 aml_console_init(); 73 74 /* Check that params passed from BL2 are not NULL. */ 75 from_bl2 = (struct gxl_bl31_param *) arg0; 76 77 /* Check params passed from BL2 are not NULL. */ 78 assert(from_bl2 != NULL); 79 assert(from_bl2->h.type == PARAM_BL31); 80 assert(from_bl2->h.version >= VERSION_1); 81 82 /* 83 * Copy BL33 entry point information. It is stored in Secure RAM, in 84 * BL2's address space. 85 */ 86 bl33_image_ep_info = *from_bl2->bl33_ep_info; 87 88 if (bl33_image_ep_info.pc == 0U) { 89 ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); 90 panic(); 91 } 92 93 bl30_image_info = *from_bl2->scp_image_info[0]; 94 bl301_image_info = *from_bl2->scp_image_info[1]; 95 } 96 97 void bl31_plat_arch_setup(void) 98 { 99 aml_setup_page_tables(); 100 101 enable_mmu_el3(0); 102 } 103 104 static inline bool gxl_scp_ready(void) 105 { 106 return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT)); 107 } 108 109 static inline void gxl_scp_boot(void) 110 { 111 aml_scpi_upload_scp_fw(bl30_image_info.image_base, 112 bl30_image_info.image_size, 0); 113 aml_scpi_upload_scp_fw(bl301_image_info.image_base, 114 bl301_image_info.image_size, 1); 115 while (!gxl_scp_ready()) 116 ; 117 } 118 119 /******************************************************************************* 120 * GICv2 driver setup information 121 ******************************************************************************/ 122 static const interrupt_prop_t gxl_interrupt_props[] = { 123 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 125 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 126 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 127 INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, 128 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 129 INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, 130 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 131 INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, 132 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 133 INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, 134 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 135 INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, 136 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 137 INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, 138 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 139 INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, 140 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 141 }; 142 143 static const gicv2_driver_data_t gxl_gic_data = { 144 .gicd_base = AML_GICD_BASE, 145 .gicc_base = AML_GICC_BASE, 146 .interrupt_props = gxl_interrupt_props, 147 .interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props), 148 }; 149 150 void bl31_platform_setup(void) 151 { 152 aml_mhu_secure_init(); 153 154 gicv2_driver_init(&gxl_gic_data); 155 gicv2_distif_init(); 156 gicv2_pcpu_distif_init(); 157 gicv2_cpuif_enable(); 158 159 gxl_scp_boot(); 160 161 aml_thermal_unknown(); 162 } 163