1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/amd/versal2 8 9override NEED_BL1 := no 10override NEED_BL2 := no 11 12# A78 Erratum for SoC 13ERRATA_A78_AE_1941500 := 1 14ERRATA_A78_AE_1951502 := 1 15ERRATA_A78_AE_2376748 := 1 16ERRATA_A78_AE_2395408 := 1 17ERRATA_ABI_SUPPORT := 1 18 19# Platform Supports Armv8.2 extensions 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 2 22 23override PROGRAMMABLE_RESET_ADDRESS := 1 24PSCI_EXTENDED_STATE_ID := 1 25SEPARATE_CODE_AND_RODATA := 1 26override RESET_TO_BL31 := 1 27PL011_GENERIC_UART := 1 28IPI_CRC_CHECK := 0 29GIC_ENABLE_V4_EXTN := 0 30GICV3_SUPPORT_GIC600 := 1 31TFA_NO_PM := 0 32CPU_PWRDWN_SGI ?= 6 33$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI})) 34 35override CTX_INCLUDE_AARCH32_REGS := 0 36 37# Platform to support Dynamic XLAT Table by default 38override PLAT_XLAT_TABLES_DYNAMIC := 1 39$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) 40 41ifdef TFA_NO_PM 42 $(eval $(call add_define,TFA_NO_PM)) 43endif 44 45ifdef MEM_BASE 46 $(eval $(call add_define,MEM_BASE)) 47 48 ifndef MEM_SIZE 49 $(error "MEM_BASE defined without MEM_SIZE") 50 endif 51 $(eval $(call add_define,MEM_SIZE)) 52 53 ifdef MEM_PROGBITS_SIZE 54 $(eval $(call add_define,MEM_PROGBITS_SIZE)) 55 endif 56endif 57 58ifdef BL32_MEM_BASE 59 $(eval $(call add_define,BL32_MEM_BASE)) 60 61 ifndef BL32_MEM_SIZE 62 $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE") 63 endif 64 $(eval $(call add_define,BL32_MEM_SIZE)) 65endif 66 67ifdef IPI_CRC_CHECK 68 $(eval $(call add_define,IPI_CRC_CHECK)) 69endif 70 71USE_COHERENT_MEM := 0 72HW_ASSISTED_COHERENCY := 1 73 74CONSOLE ?= pl011 75ifeq (${CONSOLE}, $(filter ${CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 76 else 77 $(error "Please define CONSOLE") 78 endif 79 80$(eval $(call add_define_val,CONSOLE,CONSOLE_ID_${CONSOLE})) 81 82# Runtime console in default console in DEBUG build 83ifeq ($(DEBUG), 1) 84CONSOLE_RUNTIME ?= $(CONSOLE) 85endif 86 87# Runtime console 88ifdef CONSOLE_RUNTIME 89ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 90$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 91else 92 $(error "Please define CONSOLE_RUNTIME") 93endif 94endif 95 96ifeq (${TRANSFER_LIST},0) 97XILINX_OF_BOARD_DTB_ADDR ?= 0x1000000 98$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 99endif 100 101PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 102 -Iplat/xilinx/common/include/ \ 103 -Iplat/amd/common/include/ \ 104 -Iplat/xilinx/common/ipi_mailbox_service/ \ 105 -I${PLAT_PATH}/include/ \ 106 -Iplat/xilinx/versal/pm_service/ 107 108# Include GICv3 driver files 109include drivers/arm/gic/v3/gicv3.mk 110include lib/xlat_tables_v2/xlat_tables.mk 111include lib/libfdt/libfdt.mk 112 113PLAT_BL_COMMON_SOURCES := \ 114 drivers/arm/dcc/dcc_console.c \ 115 drivers/delay_timer/delay_timer.c \ 116 drivers/delay_timer/generic_delay_timer.c \ 117 ${GICV3_SOURCES} \ 118 drivers/arm/pl011/aarch64/pl011_console.S \ 119 plat/xilinx/common/plat_clkfunc.c \ 120 plat/common/aarch64/crash_console_helpers.S \ 121 plat/arm/common/arm_common.c \ 122 plat/common/plat_gicv3.c \ 123 ${PLAT_PATH}/aarch64/helpers.S \ 124 ${PLAT_PATH}/aarch64/common.c \ 125 ${PLAT_PATH}/plat_topology.c \ 126 ${XLAT_TABLES_LIB_SRCS} 127 128BL31_SOURCES += drivers/arm/cci/cci.c \ 129 lib/cpus/aarch64/cortex_a78_ae.S \ 130 lib/cpus/aarch64/cortex_a78.S \ 131 plat/common/plat_psci_common.c 132 133ifeq ($(TFA_NO_PM), 0) 134BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \ 135 plat/xilinx/common/pm_service/pm_ipi.c \ 136 ${PLAT_PATH}/plat_psci_pm.c \ 137 ${PLAT_PATH}/pm_service/pm_svc_main.c \ 138 ${PLAT_PATH}/pm_service/pm_client.c 139else 140BL31_SOURCES += ${PLAT_PATH}/plat_psci.c \ 141 drivers/scmi-msg/base.c \ 142 drivers/scmi-msg/entry.c \ 143 drivers/scmi-msg/smt.c \ 144 drivers/scmi-msg/clock.c \ 145 drivers/scmi-msg/power_domain.c \ 146 drivers/scmi-msg/reset_domain.c \ 147 ${PLAT_PATH}/scmi.c 148endif 149 150BL31_SOURCES += common/fdt_wrappers.c \ 151 plat/xilinx/common/plat_console.c \ 152 plat/xilinx/common/plat_startup.c \ 153 plat/xilinx/common/ipi.c \ 154 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 155 ${PLAT_PATH}/soc_ipi.c \ 156 plat/xilinx/common/versal.c \ 157 ${PLAT_PATH}/bl31_setup.c \ 158 common/fdt_fixup.c \ 159 common/fdt_wrappers.c \ 160 ${LIBFDT_SRCS} \ 161 ${PLAT_PATH}/sip_svc_setup.c \ 162 ${PLAT_PATH}/gicv3.c 163 164 165ifeq ($(DEBUG),1) 166BL31_SOURCES += ${PLAT_PATH}/plat_ocm_coherency.c 167endif 168 169ifeq (${ERRATA_ABI_SUPPORT}, 1) 170# enable the cpu macros for errata abi interface 171CORTEX_A78_AE_H_INC := 1 172$(eval $(call add_define, CORTEX_A78_AE_H_INC)) 173endif 174 175# Enable Handoff protocol using transfer lists 176TRANSFER_LIST ?= 0 177 178ifeq (${TRANSFER_LIST},1) 179include lib/transfer_list/transfer_list.mk 180BL31_SOURCES += plat/amd/common/plat_fdt.c 181BL31_SOURCES += plat/amd/common/plat_xfer_list.c 182else 183BL31_SOURCES += plat/xilinx/common/plat_fdt.c 184endif 185 186XLNX_DT_CFG ?= 1 187ifeq (${TRANSFER_LIST},0) 188ifndef XILINX_OF_BOARD_DTB_ADDR 189XLNX_DT_CFG := 0 190endif 191endif 192$(eval $(call add_define,XLNX_DT_CFG)) 193 194ifdef CUSTOM_PKG_PATH 195include $(CUSTOM_PKG_PATH)/custom_pkg.mk 196else 197BL31_SOURCES += plat/xilinx/common/custom_sip_svc.c 198endif 199