xref: /rk3399_ARM-atf/plat/amd/versal2/platform.mk (revision d75ff91527c8c8a97411f1196b42a36a210a3f20)
1c97857dbSAmit Nagal# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
2c97857dbSAmit Nagal# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
35cb9125eSMaheedhar Bollapalli# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
4c97857dbSAmit Nagal#
5c97857dbSAmit Nagal# SPDX-License-Identifier: BSD-3-Clause
6c97857dbSAmit Nagal
7c97857dbSAmit NagalPLAT_PATH := plat/amd/versal2
8c97857dbSAmit Nagal
91fbe81feSAmit Nagaloverride NEED_BL1 := no
101fbe81feSAmit Nagaloverride NEED_BL2 := no
111fbe81feSAmit Nagal
12c97857dbSAmit Nagal# A78 Erratum for SoC
13c97857dbSAmit NagalERRATA_A78_AE_1941500 := 1
14c97857dbSAmit NagalERRATA_A78_AE_1951502 := 1
15c97857dbSAmit NagalERRATA_A78_AE_2376748 := 1
16c97857dbSAmit NagalERRATA_A78_AE_2395408 := 1
17c97857dbSAmit NagalERRATA_ABI_SUPPORT    := 1
18c97857dbSAmit Nagal
19c97857dbSAmit Nagal# Platform Supports Armv8.2 extensions
20c97857dbSAmit NagalARM_ARCH_MAJOR := 8
21c97857dbSAmit NagalARM_ARCH_MINOR := 2
22c97857dbSAmit Nagal
23c97857dbSAmit Nagaloverride PROGRAMMABLE_RESET_ADDRESS := 1
24c97857dbSAmit NagalPSCI_EXTENDED_STATE_ID := 1
25c97857dbSAmit NagalSEPARATE_CODE_AND_RODATA := 1
26c97857dbSAmit Nagaloverride RESET_TO_BL31 := 1
27c97857dbSAmit NagalPL011_GENERIC_UART := 1
28c97857dbSAmit NagalIPI_CRC_CHECK := 0
29c97857dbSAmit NagalGIC_ENABLE_V4_EXTN :=  0
30c97857dbSAmit NagalGICV3_SUPPORT_GIC600 := 1
310cc5e210SSenthil Nathan ThangarajTFA_NO_PM := 0
32414cf08bSSenthil Nathan ThangarajCPU_PWRDWN_SGI ?= 6
33414cf08bSSenthil Nathan Thangaraj$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI}))
34c97857dbSAmit Nagal
35c97857dbSAmit Nagaloverride CTX_INCLUDE_AARCH32_REGS    := 0
36c97857dbSAmit Nagal
379aa71f48SAkshay Belsare# Platform to support Dynamic XLAT Table by default
389aa71f48SAkshay Belsareoverride PLAT_XLAT_TABLES_DYNAMIC := 1
399aa71f48SAkshay Belsare$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
409aa71f48SAkshay Belsare
41414cf08bSSenthil Nathan Thangarajifdef TFA_NO_PM
42414cf08bSSenthil Nathan Thangaraj   $(eval $(call add_define,TFA_NO_PM))
43414cf08bSSenthil Nathan Thangarajendif
44414cf08bSSenthil Nathan Thangaraj
45c97857dbSAmit Nagalifdef MEM_BASE
46c97857dbSAmit Nagal    $(eval $(call add_define,MEM_BASE))
47c97857dbSAmit Nagal
48c97857dbSAmit Nagal    ifndef MEM_SIZE
491e2a5e28SMichal Simek        $(error "MEM_BASE defined without MEM_SIZE")
50c97857dbSAmit Nagal    endif
51c97857dbSAmit Nagal    $(eval $(call add_define,MEM_SIZE))
52c97857dbSAmit Nagal
53c97857dbSAmit Nagal    ifdef MEM_PROGBITS_SIZE
54c97857dbSAmit Nagal        $(eval $(call add_define,MEM_PROGBITS_SIZE))
55c97857dbSAmit Nagal    endif
56c97857dbSAmit Nagalendif
57c97857dbSAmit Nagal
58c97857dbSAmit Nagalifdef BL32_MEM_BASE
59c97857dbSAmit Nagal    $(eval $(call add_define,BL32_MEM_BASE))
60c97857dbSAmit Nagal
61c97857dbSAmit Nagal    ifndef BL32_MEM_SIZE
621e2a5e28SMichal Simek        $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE")
63c97857dbSAmit Nagal    endif
64c97857dbSAmit Nagal    $(eval $(call add_define,BL32_MEM_SIZE))
65c97857dbSAmit Nagalendif
66c97857dbSAmit Nagal
67c97857dbSAmit Nagalifdef IPI_CRC_CHECK
68c97857dbSAmit Nagal    $(eval $(call add_define,IPI_CRC_CHECK))
69c97857dbSAmit Nagalendif
70c97857dbSAmit Nagal
71c97857dbSAmit NagalUSE_COHERENT_MEM := 0
72c97857dbSAmit NagalHW_ASSISTED_COHERENCY := 1
73c97857dbSAmit Nagal
742333ab4cSMaheedhar BollapalliCONSOLE  ?=      pl011
752333ab4cSMaheedhar Bollapalliifeq (${CONSOLE}, $(filter ${CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none))
76c97857dbSAmit Nagal	else
772333ab4cSMaheedhar Bollapalli	  $(error "Please define CONSOLE")
78c97857dbSAmit Nagal  endif
79c97857dbSAmit Nagal
802333ab4cSMaheedhar Bollapalli$(eval $(call add_define_val,CONSOLE,CONSOLE_ID_${CONSOLE}))
8111964742SMaheedhar Bollapalli
8211964742SMaheedhar Bollapalli# Runtime console in default console in DEBUG build
8311964742SMaheedhar Bollapalliifeq ($(DEBUG), 1)
8411964742SMaheedhar BollapalliCONSOLE_RUNTIME ?= pl011
8511964742SMaheedhar Bollapalliendif
8611964742SMaheedhar Bollapalli
8711964742SMaheedhar Bollapalli# Runtime console
8811964742SMaheedhar Bollapalliifdef CONSOLE_RUNTIME
8911964742SMaheedhar Bollapalliifeq 	(${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb))
9011964742SMaheedhar Bollapalli$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
9111964742SMaheedhar Bollapallielse
9211964742SMaheedhar Bollapalli	$(error "Please define CONSOLE_RUNTIME")
9311964742SMaheedhar Bollapalliendif
9411964742SMaheedhar Bollapalliendif
9511964742SMaheedhar Bollapalli
965cb9125eSMaheedhar Bollapalliifeq (${TRANSFER_LIST},0)
975cb9125eSMaheedhar BollapalliXILINX_OF_BOARD_DTB_ADDR ?= 0x1000000
98c97857dbSAmit Nagal$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
99c97857dbSAmit Nagalendif
100c97857dbSAmit Nagal
101c97857dbSAmit NagalPLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
102c97857dbSAmit Nagal				-Iplat/xilinx/common/include/			\
103c41edd80SMaheedhar Bollapalli				-Iplat/amd/common/include/			\
104c97857dbSAmit Nagal				-Iplat/xilinx/common/ipi_mailbox_service/	\
105c97857dbSAmit Nagal				-I${PLAT_PATH}/include/				\
106c97857dbSAmit Nagal				-Iplat/xilinx/versal/pm_service/
107c97857dbSAmit Nagal
108c97857dbSAmit Nagal# Include GICv3 driver files
109c97857dbSAmit Nagalinclude drivers/arm/gic/v3/gicv3.mk
110c97857dbSAmit Nagalinclude lib/xlat_tables_v2/xlat_tables.mk
111c97857dbSAmit Nagalinclude lib/libfdt/libfdt.mk
112c97857dbSAmit Nagal
113c97857dbSAmit NagalPLAT_BL_COMMON_SOURCES	:=	\
114c97857dbSAmit Nagal				drivers/arm/dcc/dcc_console.c			\
115c97857dbSAmit Nagal				drivers/delay_timer/delay_timer.c		\
116c97857dbSAmit Nagal				drivers/delay_timer/generic_delay_timer.c	\
117c97857dbSAmit Nagal				${GICV3_SOURCES}				\
118c97857dbSAmit Nagal				drivers/arm/pl011/aarch64/pl011_console.S	\
119f2ae203aSJay Buddhabhatti				plat/xilinx/common/plat_clkfunc.c		\
120c97857dbSAmit Nagal				plat/common/aarch64/crash_console_helpers.S	\
121c97857dbSAmit Nagal				plat/arm/common/arm_common.c			\
122c97857dbSAmit Nagal				plat/common/plat_gicv3.c			\
123c97857dbSAmit Nagal				${PLAT_PATH}/aarch64/helpers.S			\
124c97857dbSAmit Nagal				${PLAT_PATH}/aarch64/common.c			\
125c97857dbSAmit Nagal				${PLAT_PATH}/plat_topology.c                    \
126c97857dbSAmit Nagal				${XLAT_TABLES_LIB_SRCS}
127c97857dbSAmit Nagal
128c97857dbSAmit NagalBL31_SOURCES		+=	drivers/arm/cci/cci.c				\
129c97857dbSAmit Nagal				lib/cpus/aarch64/cortex_a78_ae.S		\
130c97857dbSAmit Nagal				lib/cpus/aarch64/cortex_a78.S			\
131*d75ff915SPrasad Kummari				plat/common/plat_psci_common.c
132c97857dbSAmit Nagal
133414cf08bSSenthil Nathan Thangarajifeq ($(TFA_NO_PM), 0)
134414cf08bSSenthil Nathan ThangarajBL31_SOURCES		+=	plat/xilinx/common/pm_service/pm_api_sys.c	\
135414cf08bSSenthil Nathan Thangaraj				plat/xilinx/common/pm_service/pm_ipi.c		\
136414cf08bSSenthil Nathan Thangaraj				${PLAT_PATH}/plat_psci_pm.c			\
1370cc5e210SSenthil Nathan Thangaraj				${PLAT_PATH}/pm_service/pm_svc_main.c	\
138414cf08bSSenthil Nathan Thangaraj				${PLAT_PATH}/pm_service/pm_client.c
139414cf08bSSenthil Nathan Thangarajelse
140*d75ff915SPrasad KummariBL31_SOURCES		+=	${PLAT_PATH}/plat_psci.c			\
141*d75ff915SPrasad Kummari				drivers/scmi-msg/base.c				\
142*d75ff915SPrasad Kummari				drivers/scmi-msg/entry.c			\
143*d75ff915SPrasad Kummari				drivers/scmi-msg/smt.c				\
144*d75ff915SPrasad Kummari				drivers/scmi-msg/clock.c			\
145*d75ff915SPrasad Kummari				drivers/scmi-msg/power_domain.c			\
146*d75ff915SPrasad Kummari				drivers/scmi-msg/reset_domain.c			\
147*d75ff915SPrasad Kummari				${PLAT_PATH}/scmi.c
148414cf08bSSenthil Nathan Thangarajendif
149414cf08bSSenthil Nathan Thangaraj
150414cf08bSSenthil Nathan ThangarajBL31_SOURCES		+=	common/fdt_wrappers.c                           \
15111964742SMaheedhar Bollapalli				plat/xilinx/common/plat_console.c               \
152c97857dbSAmit Nagal				plat/xilinx/common/plat_startup.c		\
153c97857dbSAmit Nagal				plat/xilinx/common/ipi.c			\
154c97857dbSAmit Nagal				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c	\
155c97857dbSAmit Nagal				${PLAT_PATH}/soc_ipi.c				\
156c97857dbSAmit Nagal				plat/xilinx/common/versal.c			\
157c97857dbSAmit Nagal				${PLAT_PATH}/bl31_setup.c			\
158c97857dbSAmit Nagal				common/fdt_fixup.c				\
15942488064SAndre Przywara				common/fdt_wrappers.c				\
160c97857dbSAmit Nagal				${LIBFDT_SRCS}					\
161c97857dbSAmit Nagal				${PLAT_PATH}/sip_svc_setup.c			\
162c97857dbSAmit Nagal				${PLAT_PATH}/gicv3.c
163c97857dbSAmit Nagal
164c3ab09d1SSaivardhan Thatikonda
165c3ab09d1SSaivardhan Thatikondaifeq ($(DEBUG),1)
166c3ab09d1SSaivardhan ThatikondaBL31_SOURCES            +=      ${PLAT_PATH}/plat_ocm_coherency.c
167c3ab09d1SSaivardhan Thatikondaendif
168c3ab09d1SSaivardhan Thatikonda
169c97857dbSAmit Nagalifeq (${ERRATA_ABI_SUPPORT}, 1)
170c97857dbSAmit Nagal# enable the cpu macros for errata abi interface
171c97857dbSAmit NagalCORTEX_A78_AE_H_INC     := 1
172c97857dbSAmit Nagal$(eval $(call add_define, CORTEX_A78_AE_H_INC))
173c97857dbSAmit Nagalendif
1741fbe81feSAmit Nagal
1751fbe81feSAmit Nagal# Enable Handoff protocol using transfer lists
1765cb9125eSMaheedhar BollapalliTRANSFER_LIST                   ?= 0
1771fbe81feSAmit Nagal
178ea453871SMaheedhar Bollapalliifeq (${TRANSFER_LIST},1)
1791fbe81feSAmit Nagalinclude lib/transfer_list/transfer_list.mk
180ea453871SMaheedhar BollapalliBL31_SOURCES           +=	plat/amd/common/plat_fdt.c
181c41edd80SMaheedhar BollapalliBL31_SOURCES           +=	plat/amd/common/plat_xfer_list.c
182ea453871SMaheedhar Bollapallielse
183ea453871SMaheedhar BollapalliBL31_SOURCES           +=	plat/xilinx/common/plat_fdt.c
184ea453871SMaheedhar Bollapalliendif
1854c5cf47fSMaheedhar Bollapalli
1864c5cf47fSMaheedhar BollapalliXLNX_DT_CFG	?= 1
1874c5cf47fSMaheedhar Bollapalliifeq (${TRANSFER_LIST},0)
1884c5cf47fSMaheedhar Bollapalliifndef XILINX_OF_BOARD_DTB_ADDR
1894c5cf47fSMaheedhar BollapalliXLNX_DT_CFG	:= 0
1904c5cf47fSMaheedhar Bollapalliendif
1914c5cf47fSMaheedhar Bollapalliendif
1924c5cf47fSMaheedhar Bollapalli$(eval $(call add_define,XLNX_DT_CFG))
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