1c97857dbSAmit Nagal# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2c97857dbSAmit Nagal# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 35cb9125eSMaheedhar Bollapalli# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4c97857dbSAmit Nagal# 5c97857dbSAmit Nagal# SPDX-License-Identifier: BSD-3-Clause 6c97857dbSAmit Nagal 7c97857dbSAmit NagalPLAT_PATH := plat/amd/versal2 8c97857dbSAmit Nagal 91fbe81feSAmit Nagaloverride NEED_BL1 := no 101fbe81feSAmit Nagaloverride NEED_BL2 := no 111fbe81feSAmit Nagal 12c97857dbSAmit Nagal# A78 Erratum for SoC 13c97857dbSAmit NagalERRATA_A78_AE_1941500 := 1 14c97857dbSAmit NagalERRATA_A78_AE_1951502 := 1 15c97857dbSAmit NagalERRATA_A78_AE_2376748 := 1 16c97857dbSAmit NagalERRATA_A78_AE_2395408 := 1 17c97857dbSAmit NagalERRATA_ABI_SUPPORT := 1 18c97857dbSAmit Nagal 19c97857dbSAmit Nagal# Platform Supports Armv8.2 extensions 20c97857dbSAmit NagalARM_ARCH_MAJOR := 8 21c97857dbSAmit NagalARM_ARCH_MINOR := 2 22c97857dbSAmit Nagal 23c97857dbSAmit Nagaloverride PROGRAMMABLE_RESET_ADDRESS := 1 24c97857dbSAmit NagalPSCI_EXTENDED_STATE_ID := 1 25c97857dbSAmit NagalSEPARATE_CODE_AND_RODATA := 1 26c97857dbSAmit Nagaloverride RESET_TO_BL31 := 1 27c97857dbSAmit NagalPL011_GENERIC_UART := 1 28c97857dbSAmit NagalIPI_CRC_CHECK := 0 29c97857dbSAmit NagalGIC_ENABLE_V4_EXTN := 0 30c97857dbSAmit NagalGICV3_SUPPORT_GIC600 := 1 310cc5e210SSenthil Nathan ThangarajTFA_NO_PM := 0 32414cf08bSSenthil Nathan ThangarajCPU_PWRDWN_SGI ?= 6 33414cf08bSSenthil Nathan Thangaraj$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI})) 34c97857dbSAmit Nagal 35c97857dbSAmit Nagaloverride CTX_INCLUDE_AARCH32_REGS := 0 36c97857dbSAmit Nagal 379aa71f48SAkshay Belsare# Platform to support Dynamic XLAT Table by default 389aa71f48SAkshay Belsareoverride PLAT_XLAT_TABLES_DYNAMIC := 1 399aa71f48SAkshay Belsare$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) 409aa71f48SAkshay Belsare 41414cf08bSSenthil Nathan Thangarajifdef TFA_NO_PM 42414cf08bSSenthil Nathan Thangaraj $(eval $(call add_define,TFA_NO_PM)) 43414cf08bSSenthil Nathan Thangarajendif 44414cf08bSSenthil Nathan Thangaraj 45c97857dbSAmit Nagalifdef MEM_BASE 46c97857dbSAmit Nagal $(eval $(call add_define,MEM_BASE)) 47c97857dbSAmit Nagal 48c97857dbSAmit Nagal ifndef MEM_SIZE 491e2a5e28SMichal Simek $(error "MEM_BASE defined without MEM_SIZE") 50c97857dbSAmit Nagal endif 51c97857dbSAmit Nagal $(eval $(call add_define,MEM_SIZE)) 52c97857dbSAmit Nagal 53c97857dbSAmit Nagal ifdef MEM_PROGBITS_SIZE 54c97857dbSAmit Nagal $(eval $(call add_define,MEM_PROGBITS_SIZE)) 55c97857dbSAmit Nagal endif 56c97857dbSAmit Nagalendif 57c97857dbSAmit Nagal 58c97857dbSAmit Nagalifdef BL32_MEM_BASE 59c97857dbSAmit Nagal $(eval $(call add_define,BL32_MEM_BASE)) 60c97857dbSAmit Nagal 61c97857dbSAmit Nagal ifndef BL32_MEM_SIZE 621e2a5e28SMichal Simek $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE") 63c97857dbSAmit Nagal endif 64c97857dbSAmit Nagal $(eval $(call add_define,BL32_MEM_SIZE)) 65c97857dbSAmit Nagalendif 66c97857dbSAmit Nagal 67c97857dbSAmit Nagalifdef IPI_CRC_CHECK 68c97857dbSAmit Nagal $(eval $(call add_define,IPI_CRC_CHECK)) 69c97857dbSAmit Nagalendif 70c97857dbSAmit Nagal 71c97857dbSAmit NagalUSE_COHERENT_MEM := 0 72c97857dbSAmit NagalHW_ASSISTED_COHERENCY := 1 73c97857dbSAmit Nagal 742333ab4cSMaheedhar BollapalliCONSOLE ?= pl011 752333ab4cSMaheedhar Bollapalliifeq (${CONSOLE}, $(filter ${CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 76c97857dbSAmit Nagal else 772333ab4cSMaheedhar Bollapalli $(error "Please define CONSOLE") 78c97857dbSAmit Nagal endif 79c97857dbSAmit Nagal 802333ab4cSMaheedhar Bollapalli$(eval $(call add_define_val,CONSOLE,CONSOLE_ID_${CONSOLE})) 8111964742SMaheedhar Bollapalli 8211964742SMaheedhar Bollapalli# Runtime console in default console in DEBUG build 8311964742SMaheedhar Bollapalliifeq ($(DEBUG), 1) 84b3555f12SPrasad KummariCONSOLE_RUNTIME ?= $(CONSOLE) 8511964742SMaheedhar Bollapalliendif 8611964742SMaheedhar Bollapalli 8711964742SMaheedhar Bollapalli# Runtime console 8811964742SMaheedhar Bollapalliifdef CONSOLE_RUNTIME 8911964742SMaheedhar Bollapalliifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 9011964742SMaheedhar Bollapalli$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 9111964742SMaheedhar Bollapallielse 9211964742SMaheedhar Bollapalli $(error "Please define CONSOLE_RUNTIME") 9311964742SMaheedhar Bollapalliendif 9411964742SMaheedhar Bollapalliendif 9511964742SMaheedhar Bollapalli 965cb9125eSMaheedhar Bollapalliifeq (${TRANSFER_LIST},0) 975cb9125eSMaheedhar BollapalliXILINX_OF_BOARD_DTB_ADDR ?= 0x1000000 98c97857dbSAmit Nagal$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 99c97857dbSAmit Nagalendif 100c97857dbSAmit Nagal 101*c7ddb0f3SPranav Tilakifeq (${SPD},spmd) 102*c7ddb0f3SPranav TilakSPMC_MANIFEST_DTB_ADDR ?= 0x9800000 103*c7ddb0f3SPranav Tilak$(eval $(call add_define,SPMC_MANIFEST_DTB_ADDR)) 104*c7ddb0f3SPranav Tilakendif 105*c7ddb0f3SPranav Tilak 106c97857dbSAmit NagalPLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 107c97857dbSAmit Nagal -Iplat/xilinx/common/include/ \ 108c41edd80SMaheedhar Bollapalli -Iplat/amd/common/include/ \ 109c97857dbSAmit Nagal -Iplat/xilinx/common/ipi_mailbox_service/ \ 110c97857dbSAmit Nagal -I${PLAT_PATH}/include/ \ 111c97857dbSAmit Nagal -Iplat/xilinx/versal/pm_service/ 112c97857dbSAmit Nagal 113c97857dbSAmit Nagal# Include GICv3 driver files 114c97857dbSAmit Nagalinclude drivers/arm/gic/v3/gicv3.mk 115c97857dbSAmit Nagalinclude lib/xlat_tables_v2/xlat_tables.mk 116c97857dbSAmit Nagalinclude lib/libfdt/libfdt.mk 117c97857dbSAmit Nagal 118c97857dbSAmit NagalPLAT_BL_COMMON_SOURCES := \ 119c97857dbSAmit Nagal drivers/arm/dcc/dcc_console.c \ 120c97857dbSAmit Nagal drivers/delay_timer/delay_timer.c \ 121c97857dbSAmit Nagal drivers/delay_timer/generic_delay_timer.c \ 122c97857dbSAmit Nagal ${GICV3_SOURCES} \ 123c97857dbSAmit Nagal drivers/arm/pl011/aarch64/pl011_console.S \ 124f2ae203aSJay Buddhabhatti plat/xilinx/common/plat_clkfunc.c \ 125c97857dbSAmit Nagal plat/common/aarch64/crash_console_helpers.S \ 126c97857dbSAmit Nagal plat/arm/common/arm_common.c \ 127c97857dbSAmit Nagal plat/common/plat_gicv3.c \ 128c97857dbSAmit Nagal ${PLAT_PATH}/aarch64/helpers.S \ 129c97857dbSAmit Nagal ${PLAT_PATH}/aarch64/common.c \ 130c97857dbSAmit Nagal ${PLAT_PATH}/plat_topology.c \ 131c97857dbSAmit Nagal ${XLAT_TABLES_LIB_SRCS} 132c97857dbSAmit Nagal 133c97857dbSAmit NagalBL31_SOURCES += drivers/arm/cci/cci.c \ 134c97857dbSAmit Nagal lib/cpus/aarch64/cortex_a78_ae.S \ 135c97857dbSAmit Nagal lib/cpus/aarch64/cortex_a78.S \ 136d75ff915SPrasad Kummari plat/common/plat_psci_common.c 137c97857dbSAmit Nagal 138414cf08bSSenthil Nathan Thangarajifeq ($(TFA_NO_PM), 0) 139414cf08bSSenthil Nathan ThangarajBL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \ 140414cf08bSSenthil Nathan Thangaraj plat/xilinx/common/pm_service/pm_ipi.c \ 141414cf08bSSenthil Nathan Thangaraj ${PLAT_PATH}/plat_psci_pm.c \ 1420cc5e210SSenthil Nathan Thangaraj ${PLAT_PATH}/pm_service/pm_svc_main.c \ 143414cf08bSSenthil Nathan Thangaraj ${PLAT_PATH}/pm_service/pm_client.c 144414cf08bSSenthil Nathan Thangarajelse 145d75ff915SPrasad KummariBL31_SOURCES += ${PLAT_PATH}/plat_psci.c \ 146d75ff915SPrasad Kummari drivers/scmi-msg/base.c \ 147d75ff915SPrasad Kummari drivers/scmi-msg/entry.c \ 148d75ff915SPrasad Kummari drivers/scmi-msg/smt.c \ 149d75ff915SPrasad Kummari drivers/scmi-msg/clock.c \ 150d75ff915SPrasad Kummari drivers/scmi-msg/power_domain.c \ 151d75ff915SPrasad Kummari drivers/scmi-msg/reset_domain.c \ 152d75ff915SPrasad Kummari ${PLAT_PATH}/scmi.c 153414cf08bSSenthil Nathan Thangarajendif 154414cf08bSSenthil Nathan Thangaraj 155414cf08bSSenthil Nathan ThangarajBL31_SOURCES += common/fdt_wrappers.c \ 15611964742SMaheedhar Bollapalli plat/xilinx/common/plat_console.c \ 157c97857dbSAmit Nagal plat/xilinx/common/plat_startup.c \ 158c97857dbSAmit Nagal plat/xilinx/common/ipi.c \ 159c97857dbSAmit Nagal plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 160c97857dbSAmit Nagal ${PLAT_PATH}/soc_ipi.c \ 161c97857dbSAmit Nagal plat/xilinx/common/versal.c \ 162c97857dbSAmit Nagal ${PLAT_PATH}/bl31_setup.c \ 163c97857dbSAmit Nagal common/fdt_fixup.c \ 16442488064SAndre Przywara common/fdt_wrappers.c \ 165c97857dbSAmit Nagal ${LIBFDT_SRCS} \ 166c97857dbSAmit Nagal ${PLAT_PATH}/sip_svc_setup.c \ 167c97857dbSAmit Nagal ${PLAT_PATH}/gicv3.c 168c97857dbSAmit Nagal 169*c7ddb0f3SPranav Tilakifeq (${SPD},spmd) 170*c7ddb0f3SPranav TilakBL31_SOURCES += plat/common/plat_spmd_manifest.c \ 171*c7ddb0f3SPranav Tilak common/uuid.c \ 172*c7ddb0f3SPranav Tilak ${LIBFDT_SRCS} \ 173*c7ddb0f3SPranav Tilak ${FDT_WRAPPERS_SOURCES} 174*c7ddb0f3SPranav Tilak 175*c7ddb0f3SPranav TilakARM_SPMC_MANIFEST_DTS := ${PLAT_PATH}/spmc_sel1_optee_manifest.dts 176*c7ddb0f3SPranav Tilak 177*c7ddb0f3SPranav TilakFDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 178*c7ddb0f3SPranav Tilak 179*c7ddb0f3SPranav TilakVERSAL2_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 180*c7ddb0f3SPranav Tilak 181*c7ddb0f3SPranav Tilak$(eval $(call TOOL_ADD_PAYLOAD,${VERSAL2_TOS_FW_CONFIG},--tos-fw-config,${VERSAL2_TOS_FW_CONFIG})) 182*c7ddb0f3SPranav Tilakendif 183c3ab09d1SSaivardhan Thatikonda 184c3ab09d1SSaivardhan Thatikondaifeq ($(DEBUG),1) 185c3ab09d1SSaivardhan ThatikondaBL31_SOURCES += ${PLAT_PATH}/plat_ocm_coherency.c 186c3ab09d1SSaivardhan Thatikondaendif 187c3ab09d1SSaivardhan Thatikonda 188c97857dbSAmit Nagalifeq (${ERRATA_ABI_SUPPORT}, 1) 189c97857dbSAmit Nagal# enable the cpu macros for errata abi interface 190c97857dbSAmit NagalCORTEX_A78_AE_H_INC := 1 191c97857dbSAmit Nagal$(eval $(call add_define, CORTEX_A78_AE_H_INC)) 192c97857dbSAmit Nagalendif 1931fbe81feSAmit Nagal 1941fbe81feSAmit Nagal# Enable Handoff protocol using transfer lists 1955cb9125eSMaheedhar BollapalliTRANSFER_LIST ?= 0 1961fbe81feSAmit Nagal 197ea453871SMaheedhar Bollapalliifeq (${TRANSFER_LIST},1) 1981fbe81feSAmit Nagalinclude lib/transfer_list/transfer_list.mk 199ea453871SMaheedhar BollapalliBL31_SOURCES += plat/amd/common/plat_fdt.c 200c41edd80SMaheedhar BollapalliBL31_SOURCES += plat/amd/common/plat_xfer_list.c 201ea453871SMaheedhar Bollapallielse 202ea453871SMaheedhar BollapalliBL31_SOURCES += plat/xilinx/common/plat_fdt.c 203ea453871SMaheedhar Bollapalliendif 2044c5cf47fSMaheedhar Bollapalli 2054c5cf47fSMaheedhar BollapalliXLNX_DT_CFG ?= 1 2064c5cf47fSMaheedhar Bollapalliifeq (${TRANSFER_LIST},0) 2074c5cf47fSMaheedhar Bollapalliifndef XILINX_OF_BOARD_DTB_ADDR 2084c5cf47fSMaheedhar BollapalliXLNX_DT_CFG := 0 2094c5cf47fSMaheedhar Bollapalliendif 2104c5cf47fSMaheedhar Bollapalliendif 2114c5cf47fSMaheedhar Bollapalli$(eval $(call add_define,XLNX_DT_CFG)) 2124efae6abSPrasad Kummari 2134efae6abSPrasad Kummariifdef CUSTOM_PKG_PATH 2144efae6abSPrasad Kummariinclude $(CUSTOM_PKG_PATH)/custom_pkg.mk 2154efae6abSPrasad Kummarielse 2164efae6abSPrasad KummariBL31_SOURCES += plat/xilinx/common/custom_sip_svc.c 2174efae6abSPrasad Kummariendif 218