1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <plat_arm.h> 18 19 #include <plat_private.h> 20 #include <pm_defs.h> 21 22 #define PM_RET_ERROR_NOFEATURE U(19) 23 #define ALWAYSTRUE true 24 #define LINEAR_MODE BIT(1) 25 26 static uintptr_t _sec_entry; 27 28 static void zynqmp_cpu_standby(plat_local_state_t cpu_state) 29 { 30 dsb(); 31 wfi(); 32 } 33 34 #define MPIDR_MT_BIT (24) 35 36 static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) 37 { 38 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT); 39 int32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; 40 int32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; 41 uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0; 42 uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U); 43 int32_t ret = PSCI_E_SUCCESS; 44 45 VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n", 46 __func__, mpidr, cpu_id, cpu, cluster); 47 48 if (cpu_id == -1) { 49 ret = PSCI_E_INTERN_FAIL; 50 goto exit_label; 51 } 52 53 if (cluster > 3U) { 54 panic(); 55 } 56 57 apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + ((uint64_t)cluster * APU_PCLI_CLUSTER_STEP); 58 apu_cluster_base = APU_CLUSTER0 + ((uint64_t)cluster * APU_CLUSTER_STEP); 59 60 /* Enable clock */ 61 mmio_setbits_32(PSX_CRF + ACPU0_CLK_CTRL + ((uint64_t)cluster * 0x4U), ACPU_CLK_CTRL_CLKACT); 62 63 /* Enable cluster states */ 64 mmio_setbits_32(apu_pcli_cluster + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_SET); 65 mmio_setbits_32(apu_pcli_cluster + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); 66 67 /* assert core reset */ 68 mmio_setbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); 69 70 /* program RVBAR */ 71 mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3), 72 (uint32_t)_sec_entry); 73 mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3), 74 (uint32_t)(_sec_entry >> 32)); 75 76 /* de-assert core reset */ 77 mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); 78 79 /* clear cluster resets */ 80 mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_WARM_RESET); 81 mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_COLD_RESET); 82 83 apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + 84 (APU_PCLI_CLUSTER_CPU_STEP * cluster); 85 86 mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR); 87 mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); 88 89 exit_label: 90 return ret; 91 } 92 93 static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state) 94 { 95 plat_gic_cpuif_disable(); 96 } 97 98 static void __dead2 zynqmp_nopmu_system_reset(void) 99 { 100 while (ALWAYSTRUE) { 101 wfi(); 102 } 103 } 104 105 static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) 106 { 107 int32_t ret = PSCI_E_INVALID_ADDRESS; 108 109 VERBOSE("Validate ns_entry point %lx\n", ns_entrypoint); 110 111 if ((ns_entrypoint) != 0U) { 112 ret = PSCI_E_SUCCESS; 113 } 114 115 return ret; 116 } 117 118 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 119 { 120 plat_gic_pcpu_init(); 121 plat_gic_cpuif_enable(); 122 } 123 124 static void __dead2 zynqmp_system_off(void) 125 { 126 while (ALWAYSTRUE) { 127 wfi(); 128 } 129 } 130 131 static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) 132 { 133 return PSCI_E_SUCCESS; 134 } 135 136 static const struct plat_psci_ops _nopmc_psci_ops = { 137 .cpu_standby = zynqmp_cpu_standby, 138 .pwr_domain_on = zynqmp_nopmu_pwr_domain_on, 139 .pwr_domain_off = zynqmp_nopmu_pwr_domain_off, 140 .system_reset = zynqmp_nopmu_system_reset, 141 .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, 142 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 143 .system_off = zynqmp_system_off, 144 .validate_power_state = zynqmp_validate_power_state, 145 }; 146 147 /******************************************************************************* 148 * Export the platform specific power ops. 149 ******************************************************************************/ 150 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 151 const struct plat_psci_ops **psci_ops) 152 { 153 _sec_entry = sec_entrypoint; 154 155 VERBOSE("Setting up entry point %lx\n", _sec_entry); 156 157 *psci_ops = &_nopmc_psci_ops; 158 159 return 0; 160 } 161 162 int sip_svc_setup_init(void) 163 { 164 return 0; 165 } 166 167 static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id, 168 uint32_t arg1, uint32_t arg2) 169 { 170 int32_t ret = 0; 171 VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1); 172 173 switch (ioctl_id) { 174 case IOCTL_OSPI_MUX_SELECT: 175 if ((arg1 == 0) || (arg1 == 1)) { 176 mmio_clrsetbits_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, LINEAR_MODE, 177 (arg1 ? LINEAR_MODE : 0)); 178 } else { 179 ret = PM_RET_ERROR_ARGS; 180 } 181 break; 182 case IOCTL_UFS_TXRX_CFGRDY_GET: 183 ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY); 184 break; 185 case IOCTL_UFS_SRAM_CSR_SEL: 186 if (arg1 == 1U) { 187 ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_SRAM_CSR); 188 } else if (arg1 == 0U) { 189 mmio_write_32(PMXC_IOU_SLCR_SRAM_CSR, arg2); 190 } 191 break; 192 case IOCTL_USB_SET_STATE: 193 break; 194 default: 195 ret = PM_RET_ERROR_NOFEATURE; 196 break; 197 } 198 199 return ret; 200 } 201 202 static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 203 uint64_t x4, const void *cookie, void *handle, uint64_t flags) 204 { 205 int32_t ret; 206 uint32_t arg[4], api_id; 207 208 arg[0] = (uint32_t)x1; 209 arg[1] = (uint32_t)(x1 >> 32); 210 arg[2] = (uint32_t)x2; 211 arg[3] = (uint32_t)(x2 >> 32); 212 213 api_id = smc_fid & FUNCID_NUM_MASK; 214 VERBOSE("%s: smc_fid: %x, api_id=0x%x\n", __func__, smc_fid, api_id); 215 216 switch (api_id) { 217 case PM_IOCTL: 218 { 219 ret = no_pm_ioctl(arg[0], arg[1], arg[2], arg[3]); 220 /* Firmware driver expects return code in upper 32 bits and 221 * status in lower 32 bits. 222 * status is always SUCCESS(0) for mmio low level register 223 * r/w calls and return value is the value returned from 224 * no_pm_ioctl 225 */ 226 SMC_RET1(handle, ((uint64_t)ret << 32)); 227 } 228 case PM_GET_CHIPID: 229 { 230 uint32_t idcode, version_type; 231 232 idcode = mmio_read_32(PMC_TAP); 233 version_type = mmio_read_32(PMC_TAP_VERSION); 234 SMC_RET2(handle, ((uint64_t)idcode << 32), version_type); 235 } 236 default: 237 WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); 238 SMC_RET1(handle, SMC_UNK); 239 } 240 } 241 242 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 243 const void *cookie, void *handle, uint64_t flags) 244 { 245 return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 246 } 247