1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Macros IDs for AMD Versal Gen 2 4 * 5 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 */ 9 10 #ifndef _VERSAL2_SCMI_H 11 #define _VERSAL2_SCMI_H 12 13 #define CLK_GEM0_0 0U 14 #define CLK_GEM0_1 1U 15 #define CLK_GEM0_2 2U 16 #define CLK_GEM0_3 3U 17 #define CLK_GEM0_4 4U 18 #define CLK_GEM1_0 5U 19 #define CLK_GEM1_1 6U 20 #define CLK_GEM1_2 7U 21 #define CLK_GEM1_3 8U 22 #define CLK_GEM1_4 9U 23 #define CLK_SERIAL0_0 10U 24 #define CLK_SERIAL0_1 11U 25 #define CLK_SERIAL1_0 12U 26 #define CLK_SERIAL1_1 13U 27 #define CLK_UFS0_0 14U 28 #define CLK_UFS0_1 15U 29 #define CLK_UFS0_2 16U 30 #define CLK_USB0_0 17U 31 #define CLK_USB0_1 18U 32 #define CLK_USB0_2 19U 33 #define CLK_USB1_0 20U 34 #define CLK_USB1_1 21U 35 #define CLK_USB1_2 22U 36 #define CLK_MMC0_0 23U 37 #define CLK_MMC0_1 24U 38 #define CLK_MMC0_2 25U 39 #define CLK_MMC1_0 26U 40 #define CLK_MMC1_1 27U 41 #define CLK_MMC1_2 28U 42 #define CLK_TTC0_0 29U 43 #define CLK_TTC1_0 30U 44 #define CLK_TTC2_0 31U 45 #define CLK_TTC3_0 32U 46 #define CLK_TTC4_0 33U 47 #define CLK_TTC5_0 34U 48 #define CLK_TTC6_0 35U 49 #define CLK_TTC7_0 36U 50 #define CLK_I2C0_0 37U 51 #define CLK_I2C1_0 38U 52 #define CLK_I2C2_0 39U 53 #define CLK_I2C3_0 40U 54 #define CLK_I2C4_0 41U 55 #define CLK_I2C5_0 42U 56 #define CLK_I2C6_0 43U 57 #define CLK_I2C7_0 44U 58 #define CLK_OSPI0_0 45U 59 #define CLK_QSPI0_0 46U 60 #define CLK_QSPI0_1 47U 61 #define CLK_WWDT0_0 48U 62 #define CLK_WWDT1_0 49U 63 #define CLK_WWDT2_0 50U 64 #define CLK_WWDT3_0 51U 65 #define CLK_ADMA0_0 52U 66 #define CLK_ADMA0_1 53U 67 #define CLK_ADMA1_0 54U 68 #define CLK_ADMA1_1 55U 69 #define CLK_ADMA2_0 56U 70 #define CLK_ADMA2_1 57U 71 #define CLK_ADMA3_0 58U 72 #define CLK_ADMA3_1 59U 73 #define CLK_ADMA4_0 60U 74 #define CLK_ADMA4_1 61U 75 #define CLK_ADMA5_0 62U 76 #define CLK_ADMA5_1 63U 77 #define CLK_ADMA6_0 64U 78 #define CLK_ADMA6_1 65U 79 #define CLK_ADMA7_0 66U 80 #define CLK_ADMA7_1 67U 81 #define CLK_CAN0_0 68U 82 #define CLK_CAN0_1 69U 83 #define CLK_CAN1_0 70U 84 #define CLK_CAN1_1 71U 85 #define CLK_CAN2_0 72U 86 #define CLK_CAN2_1 73U 87 #define CLK_CAN3_0 74U 88 #define CLK_CAN3_1 75U 89 #define CLK_PS_GPIO_0 76U 90 #define CLK_PMC_GPIO_0 77U 91 #define CLK_SPI0_0 78U 92 #define CLK_SPI0_1 79U 93 #define CLK_SPI1_0 80U 94 #define CLK_SPI1_1 81U 95 #define CLK_I3C0_0 82U 96 #define CLK_I3C1_0 83U 97 #define CLK_I3C2_0 84U 98 #define CLK_I3C3_0 85U 99 #define CLK_I3C4_0 86U 100 #define CLK_I3C5_0 87U 101 #define CLK_I3C6_0 88U 102 #define CLK_I3C7_0 89U 103 104 #define RESET_GEM0_0 0 105 #define RESET_GEM1_0 1 106 #define RESET_SERIAL0_0 2 107 #define RESET_SERIAL1_0 3 108 #define RESET_UFS0_0 4 109 #define RESET_I2C0_0 5 110 #define RESET_I2C1_0 6 111 #define RESET_I2C2_0 7 112 #define RESET_I2C3_0 8 113 #define RESET_I2C4_0 9 114 #define RESET_I2C5_0 10 115 #define RESET_I2C6_0 11 116 #define RESET_I2C7_0 12 117 #define RESET_I2C8_0 13 118 #define RESET_OSPI0_0 14 119 #define RESET_USB0_0 15 120 #define RESET_USB0_1 16 121 #define RESET_USB0_2 17 122 #define RESET_USB1_0 18 123 #define RESET_USB1_1 19 124 #define RESET_USB1_2 20 125 #define RESET_MMC0_0 21 126 #define RESET_MMC1_0 22 127 #define RESET_SPI0_0 23 128 #define RESET_SPI1_0 24 129 #define RESET_QSPI0_0 25 130 #define RESET_I3C0_0 26 131 #define RESET_I3C1_0 27 132 #define RESET_I3C2_0 28 133 #define RESET_I3C3_0 29 134 #define RESET_I3C4_0 30 135 #define RESET_I3C5_0 31 136 #define RESET_I3C6_0 32 137 #define RESET_I3C7_0 33 138 #define RESET_I3C8_0 34 139 #define RESET_UFSPHY_0 35 140 141 #define PD_USB0 0 142 #define PD_USB1 1 143 144 #endif /* _VERSAL2_SCMI_H */ 145