1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef DEF_H 10 #define DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2 16 17 /* List all consoles */ 18 #define CONSOLE_ID_pl011 U(1) 19 #define CONSOLE_ID_pl011_0 U(1) 20 #define CONSOLE_ID_pl011_1 U(2) 21 #define CONSOLE_ID_dcc U(3) 22 23 #define CONSOLE_IS(con) (CONSOLE_ID_ ## con == CONSOLE) 24 25 /* List all platforms */ 26 #define SILICON U(0) 27 #define SPP U(1) 28 #define EMU U(2) 29 #define QEMU U(3) 30 #define SPP_MMD U(5) 31 #define EMU_MMD U(6) 32 #define QEMU_COSIM U(7) 33 34 /* For platform detection */ 35 #define PMC_TAP U(0xF11A0000) 36 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 37 # define PLATFORM_MASK GENMASK(27U, 24U) 38 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 39 40 /* Global timer reset */ 41 #define PSX_CRF U(0xEC200000) 42 #define ACPU0_CLK_CTRL U(0x10C) 43 #define ACPU_CLK_CTRL_CLKACT BIT(25) 44 45 #define RST_APU0_OFFSET U(0x300) 46 #define RST_APU_COLD_RESET BIT(0) 47 #define RST_APU_WARN_RESET BIT(4) 48 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 49 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 50 51 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 52 53 #define APU_PCLI (0xECB10000ULL) 54 #define APU_PCLI_CPU_STEP (0x30ULL) 55 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 56 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 57 #define APU_PCLI_CLUSTER_STEP U(0x1000) 58 #define PCLI_PREQ_OFFSET U(0x4) 59 #define PREQ_CHANGE_REQUEST BIT(0) 60 #define PCLI_PSTATE_OFFSET U(0x8) 61 #define PCLI_PSTATE_VAL_SET U(0x48) 62 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 63 64 /* Firmware Image Package */ 65 #define PRIMARY_CPU U(0) 66 67 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 68 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 69 (APU_PCLI_CPU_STEP * (cpu_id)))) 70 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 71 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 72 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 73 (APU_PCLI_CPU_STEP * (cpu_id)))) 74 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 75 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 76 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 77 (APU_PCLI_CPU_STEP * (cpu_id)))) 78 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 79 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 80 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 81 (APU_PCLI_CPU_STEP * (cpu_id)))) 82 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 83 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 84 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 85 (APU_PCLI_CPU_STEP * (cpu_id)))) 86 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 87 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 88 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 89 (APU_PCLI_CPU_STEP * (cpu_id)))) 90 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 91 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 92 93 /******************************************************************************* 94 * memory map related constants 95 ******************************************************************************/ 96 /* IPP 1.2/SPP 0.9 mapping */ 97 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 98 #define DEVICE0_SIZE U(0x08000000) 99 #define DEVICE1_BASE U(0xE2000000) /* gic */ 100 #define DEVICE1_SIZE U(0x00800000) 101 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 102 #define DEVICE2_SIZE U(0x01000000) 103 #define CRF_BASE U(0xFD1A0000) 104 #define CRF_SIZE U(0x00600000) 105 #define IPI_BASE U(0xEB300000) 106 #define IPI_SIZE U(0x00100000) 107 108 /* CRL */ 109 #define CRL U(0xEB5E0000) 110 #define CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 111 #define CRL_RST_TIMESTAMP_OFFSET U(0x348) 112 113 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 114 115 /* IOU SCNTRS */ 116 #define IOU_SCNTRS U(0xEC920000) 117 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 118 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 119 120 #define IOU_SCNTRS_CONTROL_EN U(1) 121 122 #define APU_CLUSTER0 U(0xECC00000) 123 #define APU_RVBAR_L_0 U(0x40) 124 #define APU_RVBAR_H_0 U(0x44) 125 #define APU_CLUSTER_STEP U(0x100000) 126 127 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 128 #define PMXC_IOU_SLCR_SRAM_CSR U(0xF106104C) 129 #define PMXC_IOU_SLCR_PHY_RESET U(0xF1061050) 130 #define PMXC_IOU_SLCR_TX_RX_CONFIG_RDY U(0xF1061054) 131 #define PMXC_CRP_RST_UFS U(0xF1260340) 132 133 /******************************************************************************* 134 * IRQ constants 135 ******************************************************************************/ 136 #define IRQ_SEC_PHY_TIMER U(29) 137 138 /******************************************************************************* 139 * UART related constants 140 ******************************************************************************/ 141 #define UART0_BASE U(0xF1920000) 142 #define UART1_BASE U(0xF1930000) 143 144 #define UART_BAUDRATE 115200 145 146 #if CONSOLE_IS(pl011_1) 147 #define UART_BASE UART1_BASE 148 #else 149 /* Default console is UART0 */ 150 #define UART_BASE UART0_BASE 151 #endif 152 153 #endif /* DEF_H */ 154