1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SUNXI_MMAP_H__ 8 #define __SUNXI_MMAP_H__ 9 10 /* Memory regions */ 11 #define SUNXI_ROM_BASE 0x00000000 12 #define SUNXI_ROM_SIZE 0x00010000 13 #define SUNXI_SRAM_BASE 0x00010000 14 #define SUNXI_SRAM_SIZE 0x00044000 15 #define SUNXI_SRAM_A1_BASE 0x00010000 16 #define SUNXI_SRAM_A1_SIZE 0x00008000 17 #define SUNXI_SRAM_A2_BASE 0x00044000 18 #define SUNXI_SRAM_A2_SIZE 0x00010000 19 #define SUNXI_SRAM_C_BASE 0x00018000 20 #define SUNXI_SRAM_C_SIZE 0x0001c000 21 #define SUNXI_DEV_BASE 0x01000000 22 #define SUNXI_DEV_SIZE 0x01000000 23 #define SUNXI_DRAM_BASE 0x40000000 24 #define SUNXI_DRAM_SIZE 0x80000000 25 26 /* Memory-mapped devices */ 27 #define SUNXI_CPU_MBIST_BASE 0x01502000 28 #define SUNXI_CPUCFG_BASE 0x01700000 29 #define SUNXI_SYSCON_BASE 0x01c00000 30 #define SUNXI_SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 31 #define SUNXI_DMA_BASE 0x01c02000 32 #define SUNXI_KEYMEM_BASE 0x01c0b000 33 #define SUNXI_SMHC0_BASE 0x01c0f000 34 #define SUNXI_SMHC1_BASE 0x01c10000 35 #define SUNXI_SMHC2_BASE 0x01c11000 36 #define SUNXI_SID_BASE 0x01c14000 37 #define SUNXI_MSGBOX_BASE 0x01c17000 38 #define SUNXI_SPINLOCK_BASE 0x01c18000 39 #define SUNXI_CCU_BASE 0x01c20000 40 #define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x2f0) 41 #define SUNXI_PIO_BASE 0x01c20800 42 #define SUNXI_TIMER_BASE 0x01c20c00 43 #define SUNXI_WDOG_BASE 0x01c20ca0 44 #define SUNXI_SPC_BASE 0x01c23400 45 #define SUNXI_THS_BASE 0x01c25000 46 #define SUNXI_UART0_BASE 0x01c28000 47 #define SUNXI_UART1_BASE 0x01c28400 48 #define SUNXI_UART2_BASE 0x01c28800 49 #define SUNXI_UART3_BASE 0x01c28c00 50 #define SUNXI_I2C0_BASE 0x01c2ac00 51 #define SUNXI_I2C1_BASE 0x01c2b000 52 #define SUNXI_I2C2_BASE 0x01c2b400 53 #define SUNXI_DRAMCOM_BASE 0x01c62000 54 #define SUNXI_DRAMCTL_BASE 0x01c63000 55 #define SUNXI_DRAMPHY_BASE 0x01c65000 56 #define SUNXI_SPI0_BASE 0x01c68000 57 #define SUNXI_SPI1_BASE 0x01c69000 58 #define SUNXI_SCU_BASE 0x01c80000 59 #define SUNXI_GICD_BASE 0x01c81000 60 #define SUNXI_GICC_BASE 0x01c82000 61 #define SUNXI_RTC_BASE 0x01f00000 62 #define SUNXI_R_TIMER_BASE 0x01f00800 63 #define SUNXI_R_INTC_BASE 0x01f00c00 64 #define SUNXI_R_WDOG_BASE 0x01f01000 65 #define SUNXI_R_PRCM_BASE 0x01f01400 66 #define SUNXI_R_TWD_BASE 0x01f01800 67 #define SUNXI_R_CPUCFG_BASE 0x01f01c00 68 #define SUNXI_R_CIR_BASE 0x01f02000 69 #define SUNXI_R_I2C_BASE 0x01f02400 70 #define SUNXI_R_UART_BASE 0x01f02800 71 #define SUNXI_R_PIO_BASE 0x01f02c00 72 #define SUNXI_R_RSB_BASE 0x01f03400 73 #define SUNXI_R_PWM_BASE 0x01f03800 74 75 #endif /* __SUNXI_MMAP_H__ */ 76