Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow

Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow new AA64nAA32 position
fix(plat/allwinner): delay after enabling CPU power

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refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd7

refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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Merge changes I3703868b,Ie77476db into integration

* changes:
allwinner: Add SPC security setup for H6
allwinner: Add R_PRCM security setup for H6

allwinner: Add R_PRCM security setup for H6

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no ef

allwinner: Add R_PRCM security setup for H6

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.

Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86

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Merge "allwinner: Adjust SRAM A2 base to include the ARISC vectors" into integration

allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include

allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf

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Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2

Allwinner/pmic v2

allwinner: Adjust memory mapping to fit into 256MB

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if

allwinner: Adjust memory mapping to fit into 256MB

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1458 from Andre-ARM/allwinner/fixes

allwinner: various smaller fixes

allwinner: sun50i_a64: remove unneeded VER_REG offset

The relative VER_REG *offset* is the same across all known SoCs, so we
can define this offset near it's user.

Remove it from the memory map.

R

allwinner: sun50i_a64: remove unneeded VER_REG offset

The relative VER_REG *offset* is the same across all known SoCs, so we
can define this offset near it's user.

Remove it from the memory map.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1400 from Andre-ARM/allwinner/v1

Allwinner platform support

allwinner: Add security setup

Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure w

allwinner: Add security setup

Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure world.
This affects some clocks, DMA channels and the Secure Peripheral
Controller (SPC). The latter controls access to most devices, but is not
active unless booting with the secure boot fuse burnt.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Add Allwinner A64 support

The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top bo

allwinner: Add Allwinner A64 support

The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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