1*64b3d9d8SSamuel Holland /* 2*64b3d9d8SSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*64b3d9d8SSamuel Holland * 4*64b3d9d8SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*64b3d9d8SSamuel Holland */ 6*64b3d9d8SSamuel Holland 7*64b3d9d8SSamuel Holland #ifndef __SUNXI_MMAP_H__ 8*64b3d9d8SSamuel Holland #define __SUNXI_MMAP_H__ 9*64b3d9d8SSamuel Holland 10*64b3d9d8SSamuel Holland /* Memory regions */ 11*64b3d9d8SSamuel Holland #define SUNXI_ROM_BASE 0x00000000 12*64b3d9d8SSamuel Holland #define SUNXI_ROM_SIZE 0x00010000 13*64b3d9d8SSamuel Holland #define SUNXI_SRAM_BASE 0x00010000 14*64b3d9d8SSamuel Holland #define SUNXI_SRAM_SIZE 0x00044000 15*64b3d9d8SSamuel Holland #define SUNXI_SRAM_A1_BASE 0x00010000 16*64b3d9d8SSamuel Holland #define SUNXI_SRAM_A1_SIZE 0x00008000 17*64b3d9d8SSamuel Holland #define SUNXI_SRAM_A2_BASE 0x00044000 18*64b3d9d8SSamuel Holland #define SUNXI_SRAM_A2_SIZE 0x00010000 19*64b3d9d8SSamuel Holland #define SUNXI_SRAM_C_BASE 0x00018000 20*64b3d9d8SSamuel Holland #define SUNXI_SRAM_C_SIZE 0x0001c000 21*64b3d9d8SSamuel Holland #define SUNXI_DEV_BASE 0x01000000 22*64b3d9d8SSamuel Holland #define SUNXI_DEV_SIZE 0x01000000 23*64b3d9d8SSamuel Holland #define SUNXI_DRAM_BASE 0x40000000 24*64b3d9d8SSamuel Holland #define SUNXI_DRAM_SIZE 0x80000000 25*64b3d9d8SSamuel Holland 26*64b3d9d8SSamuel Holland /* Memory-mapped devices */ 27*64b3d9d8SSamuel Holland #define SUNXI_CPU_MBIST_BASE 0x01502000 28*64b3d9d8SSamuel Holland #define SUNXI_CPUCFG_BASE 0x01700000 29*64b3d9d8SSamuel Holland #define SUNXI_SYSCON_BASE 0x01c00000 30*64b3d9d8SSamuel Holland #define SUNXI_SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 31*64b3d9d8SSamuel Holland #define SUNXI_KEYMEM_BASE 0x01c0b000 32*64b3d9d8SSamuel Holland #define SUNXI_SMHC0_BASE 0x01c0f000 33*64b3d9d8SSamuel Holland #define SUNXI_SMHC1_BASE 0x01c10000 34*64b3d9d8SSamuel Holland #define SUNXI_SMHC2_BASE 0x01c11000 35*64b3d9d8SSamuel Holland #define SUNXI_SID_BASE 0x01c14000 36*64b3d9d8SSamuel Holland #define SUNXI_MSGBOX_BASE 0x01c17000 37*64b3d9d8SSamuel Holland #define SUNXI_SPINLOCK_BASE 0x01c18000 38*64b3d9d8SSamuel Holland #define SUNXI_CCU_BASE 0x01c20000 39*64b3d9d8SSamuel Holland #define SUNXI_PIO_BASE 0x01c20800 40*64b3d9d8SSamuel Holland #define SUNXI_TIMER_BASE 0x01c20c00 41*64b3d9d8SSamuel Holland #define SUNXI_WDOG_BASE 0x01c20ca0 42*64b3d9d8SSamuel Holland #define SUNXI_THS_BASE 0x01c25000 43*64b3d9d8SSamuel Holland #define SUNXI_UART0_BASE 0x01c28000 44*64b3d9d8SSamuel Holland #define SUNXI_UART1_BASE 0x01c28400 45*64b3d9d8SSamuel Holland #define SUNXI_UART2_BASE 0x01c28800 46*64b3d9d8SSamuel Holland #define SUNXI_UART3_BASE 0x01c28c00 47*64b3d9d8SSamuel Holland #define SUNXI_I2C0_BASE 0x01c2ac00 48*64b3d9d8SSamuel Holland #define SUNXI_I2C1_BASE 0x01c2b000 49*64b3d9d8SSamuel Holland #define SUNXI_I2C2_BASE 0x01c2b400 50*64b3d9d8SSamuel Holland #define SUNXI_DRAMCOM_BASE 0x01c62000 51*64b3d9d8SSamuel Holland #define SUNXI_DRAMCTL_BASE 0x01c63000 52*64b3d9d8SSamuel Holland #define SUNXI_DRAMPHY_BASE 0x01c65000 53*64b3d9d8SSamuel Holland #define SUNXI_SPI0_BASE 0x01c68000 54*64b3d9d8SSamuel Holland #define SUNXI_SPI1_BASE 0x01c69000 55*64b3d9d8SSamuel Holland #define SUNXI_SCU_BASE 0x01c80000 56*64b3d9d8SSamuel Holland #define SUNXI_GICD_BASE 0x01c81000 57*64b3d9d8SSamuel Holland #define SUNXI_GICC_BASE 0x01c82000 58*64b3d9d8SSamuel Holland #define SUNXI_RTC_BASE 0x01f00000 59*64b3d9d8SSamuel Holland #define SUNXI_R_TIMER_BASE 0x01f00800 60*64b3d9d8SSamuel Holland #define SUNXI_R_INTC_BASE 0x01f00c00 61*64b3d9d8SSamuel Holland #define SUNXI_R_WDOG_BASE 0x01f01000 62*64b3d9d8SSamuel Holland #define SUNXI_R_PRCM_BASE 0x01f01400 63*64b3d9d8SSamuel Holland #define SUNXI_R_TWD_BASE 0x01f01800 64*64b3d9d8SSamuel Holland #define SUNXI_R_CPUCFG_BASE 0x01f01c00 65*64b3d9d8SSamuel Holland #define SUNXI_R_CIR_BASE 0x01f02000 66*64b3d9d8SSamuel Holland #define SUNXI_R_I2C_BASE 0x01f02400 67*64b3d9d8SSamuel Holland #define SUNXI_R_UART_BASE 0x01f02800 68*64b3d9d8SSamuel Holland #define SUNXI_R_PIO_BASE 0x01f02c00 69*64b3d9d8SSamuel Holland #define SUNXI_R_RSB_BASE 0x01f03400 70*64b3d9d8SSamuel Holland #define SUNXI_R_PWM_BASE 0x01f03800 71*64b3d9d8SSamuel Holland 72*64b3d9d8SSamuel Holland #endif /* __SUNXI_MMAP_H__ */ 73