xref: /rk3399_ARM-atf/plat/allwinner/common/sunxi_security.c (revision 61f72a34250d063da67f4fc2b0eb8c3fda3376be)
1 /*
2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <debug.h>
8 #include <mmio.h>
9 #include <sunxi_mmap.h>
10 
11 #ifdef SUNXI_SPC_BASE
12 #define SPC_DECPORT_STA_REG(p)	(SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4)
13 #define SPC_DECPORT_SET_REG(p)	(SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8)
14 #define SPC_DECPORT_CLR_REG(p)	(SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
15 #endif
16 
17 #define R_PRCM_SEC_SWITCH_REG	0x1d0
18 #define DMA_SEC_REG		0x20
19 
20 /*
21  * Setup the peripherals to be accessible by non-secure world.
22  * This will not work for the Secure Peripherals Controller (SPC) unless
23  * a fuse it burnt (seems to be an erratum), but we do it nevertheless,
24  * to allow booting on boards using secure boot.
25  */
26 void sunxi_security_setup(void)
27 {
28 #ifdef SUNXI_SPC_BASE
29 	int i;
30 
31 	INFO("Configuring SPC Controller\n");
32 	/* SPC setup: set all devices to non-secure */
33 	for (i = 0; i < 6; i++)
34 		mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
35 #endif
36 
37 	/* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
38 	mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
39 
40 	/* set R_PRCM clocks to non-secure */
41 	mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x7);
42 
43 	/* Set all DMA channels (16 max.) to non-secure */
44 	mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);
45 }
46