1*fe753c97SSamuel Holland /* 2*fe753c97SSamuel Holland * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3*fe753c97SSamuel Holland * 4*fe753c97SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*fe753c97SSamuel Holland */ 6*fe753c97SSamuel Holland 7*fe753c97SSamuel Holland #include <arch_helpers.h> 8*fe753c97SSamuel Holland #include <common/debug.h> 9*fe753c97SSamuel Holland #include <drivers/arm/gicv2.h> 10*fe753c97SSamuel Holland #include <drivers/delay_timer.h> 11*fe753c97SSamuel Holland #include <lib/mmio.h> 12*fe753c97SSamuel Holland #include <lib/psci/psci.h> 13*fe753c97SSamuel Holland 14*fe753c97SSamuel Holland #include <sunxi_mmap.h> 15*fe753c97SSamuel Holland #include <sunxi_private.h> 16*fe753c97SSamuel Holland 17*fe753c97SSamuel Holland #define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010) 18*fe753c97SSamuel Holland #define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014) 19*fe753c97SSamuel Holland #define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018) 20*fe753c97SSamuel Holland 21*fe753c97SSamuel Holland static int sunxi_pwr_domain_on(u_register_t mpidr) 22*fe753c97SSamuel Holland { 23*fe753c97SSamuel Holland sunxi_cpu_on(mpidr); 24*fe753c97SSamuel Holland 25*fe753c97SSamuel Holland return PSCI_E_SUCCESS; 26*fe753c97SSamuel Holland } 27*fe753c97SSamuel Holland 28*fe753c97SSamuel Holland static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) 29*fe753c97SSamuel Holland { 30*fe753c97SSamuel Holland gicv2_cpuif_disable(); 31*fe753c97SSamuel Holland 32*fe753c97SSamuel Holland sunxi_cpu_power_off_self(); 33*fe753c97SSamuel Holland } 34*fe753c97SSamuel Holland 35*fe753c97SSamuel Holland static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) 36*fe753c97SSamuel Holland { 37*fe753c97SSamuel Holland gicv2_pcpu_distif_init(); 38*fe753c97SSamuel Holland gicv2_cpuif_enable(); 39*fe753c97SSamuel Holland } 40*fe753c97SSamuel Holland 41*fe753c97SSamuel Holland static void __dead2 sunxi_system_off(void) 42*fe753c97SSamuel Holland { 43*fe753c97SSamuel Holland gicv2_cpuif_disable(); 44*fe753c97SSamuel Holland 45*fe753c97SSamuel Holland /* Attempt to power down the board (may not return) */ 46*fe753c97SSamuel Holland sunxi_power_down(); 47*fe753c97SSamuel Holland 48*fe753c97SSamuel Holland /* Turn off all CPUs */ 49*fe753c97SSamuel Holland sunxi_cpu_power_off_others(); 50*fe753c97SSamuel Holland sunxi_cpu_power_off_self(); 51*fe753c97SSamuel Holland psci_power_down_wfi(); 52*fe753c97SSamuel Holland } 53*fe753c97SSamuel Holland 54*fe753c97SSamuel Holland static void __dead2 sunxi_system_reset(void) 55*fe753c97SSamuel Holland { 56*fe753c97SSamuel Holland gicv2_cpuif_disable(); 57*fe753c97SSamuel Holland 58*fe753c97SSamuel Holland /* Reset the whole system when the watchdog times out */ 59*fe753c97SSamuel Holland mmio_write_32(SUNXI_WDOG0_CFG_REG, 1); 60*fe753c97SSamuel Holland /* Enable the watchdog with the shortest timeout (0.5 seconds) */ 61*fe753c97SSamuel Holland mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1); 62*fe753c97SSamuel Holland /* Wait for twice the watchdog timeout before panicking */ 63*fe753c97SSamuel Holland mdelay(1000); 64*fe753c97SSamuel Holland 65*fe753c97SSamuel Holland ERROR("PSCI: System reset failed\n"); 66*fe753c97SSamuel Holland panic(); 67*fe753c97SSamuel Holland } 68*fe753c97SSamuel Holland 69*fe753c97SSamuel Holland static const plat_psci_ops_t sunxi_native_psci_ops = { 70*fe753c97SSamuel Holland .pwr_domain_on = sunxi_pwr_domain_on, 71*fe753c97SSamuel Holland .pwr_domain_off = sunxi_pwr_domain_off, 72*fe753c97SSamuel Holland .pwr_domain_on_finish = sunxi_pwr_domain_on_finish, 73*fe753c97SSamuel Holland .system_off = sunxi_system_off, 74*fe753c97SSamuel Holland .system_reset = sunxi_system_reset, 75*fe753c97SSamuel Holland .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, 76*fe753c97SSamuel Holland }; 77*fe753c97SSamuel Holland 78*fe753c97SSamuel Holland void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops) 79*fe753c97SSamuel Holland { 80*fe753c97SSamuel Holland *psci_ops = &sunxi_native_psci_ops; 81*fe753c97SSamuel Holland } 82