1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <lib/utils_def.h> 16 #include <plat/common/platform.h> 17 18 #include <sunxi_cpucfg.h> 19 #include <sunxi_mmap.h> 20 #include <sunxi_private.h> 21 22 #ifndef SUNXI_C0_CPU_CTRL_REG 23 #define SUNXI_C0_CPU_CTRL_REG(n) 0 24 #define SUNXI_CPU_UNK_REG(n) 0 25 #define SUNXI_CPU_CTRL_REG(n) 0 26 #endif 27 28 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) 29 { 30 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) 31 return; 32 33 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); 34 35 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); 36 } 37 38 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) 39 { 40 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) 41 return; 42 43 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); 44 45 /* Power enable sequence from original Allwinner sources */ 46 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); 47 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); 48 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); 49 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80); 50 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); 51 udelay(1); 52 } 53 54 /* We can't turn ourself off like this, but it works for other cores. */ 55 static void sunxi_cpu_off(u_register_t mpidr) 56 { 57 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 58 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 59 60 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); 61 62 if (sunxi_cpucfg_has_per_cluster_regs()) { 63 /* Deassert DBGPWRDUP */ 64 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 65 /* Activate the core output clamps, but not for core 0. */ 66 if (core != 0) { 67 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), 68 BIT(core)); 69 } 70 /* Assert CPU power-on reset */ 71 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 72 /* Remove power from the CPU */ 73 sunxi_cpu_disable_power(cluster, core); 74 } else { 75 /* power down(?) debug core */ 76 mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8)); 77 /* ??? Activate the core output clamps, but not for core 0 */ 78 if (core != 0) { 79 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(1)); 80 } 81 /* ??? Assert CPU power-on reset ??? */ 82 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); 83 /* Remove power from the CPU */ 84 sunxi_cpu_disable_power(cluster, core); 85 } 86 } 87 88 void sunxi_cpu_on(u_register_t mpidr) 89 { 90 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 91 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 92 93 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); 94 95 if (sunxi_cpucfg_has_per_cluster_regs()) { 96 /* Assert CPU core reset */ 97 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 98 /* Assert CPU power-on reset */ 99 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 100 /* Set CPU to start in AArch64 mode */ 101 mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster), 102 BIT(SUNXI_AA64nAA32_OFFSET + core)); 103 /* Apply power to the CPU */ 104 sunxi_cpu_enable_power(cluster, core); 105 /* Release the core output clamps */ 106 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 107 /* Deassert CPU power-on reset */ 108 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 109 /* Deassert CPU core reset */ 110 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 111 /* Assert DBGPWRDUP */ 112 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 113 } else { 114 /* Assert CPU core reset */ 115 mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0)); 116 /* ??? Assert CPU power-on reset ??? */ 117 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); 118 119 /* Set CPU to start in AArch64 mode */ 120 mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), BIT(0)); 121 122 /* Apply power to the CPU */ 123 sunxi_cpu_enable_power(cluster, core); 124 125 /* ??? Release the core output clamps ??? */ 126 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(1)); 127 /* ??? Deassert CPU power-on reset ??? */ 128 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); 129 /* Deassert CPU core reset */ 130 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0)); 131 /* power up(?) debug core */ 132 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8)); 133 } 134 } 135 136 void sunxi_cpu_power_off_others(void) 137 { 138 u_register_t self = read_mpidr(); 139 unsigned int cluster; 140 unsigned int core; 141 142 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) { 143 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) { 144 u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) | 145 (core << MPIDR_AFF0_SHIFT) | 146 BIT(31); 147 if (mpidr != self) 148 sunxi_cpu_off(mpidr); 149 } 150 } 151 } 152