1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <common/debug.h> 16 #include <common/fdt_fixup.h> 17 #include <common/fdt_wrappers.h> 18 #include <drivers/arm/gicv2.h> 19 #include <drivers/console.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/ti/uart/uart_16550.h> 22 #include <lib/mmio.h> 23 #include <plat/common/platform.h> 24 25 #include <sunxi_def.h> 26 #include <sunxi_mmap.h> 27 #include <sunxi_private.h> 28 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 static console_t console; 34 35 static const gicv2_driver_data_t sunxi_gic_data = { 36 .gicd_base = SUNXI_GICD_BASE, 37 .gicc_base = SUNXI_GICC_BASE, 38 }; 39 40 /* 41 * Try to find a DTB loaded in memory by previous stages. 42 * 43 * At the moment we implement a heuristic to find the DTB attached to U-Boot: 44 * U-Boot appends its DTB to the end of the image. Assuming that BL33 is 45 * U-Boot, try to find the size of the U-Boot image to learn the DTB address. 46 * The generic ARMv8 U-Boot image contains the load address and its size 47 * as u64 variables at the beginning of the image. There might be padding 48 * or other headers before that data, so scan the first 2KB after the BL33 49 * entry point to find the load address, which should be followed by the 50 * size. Adding those together gives us the address of the DTB. 51 */ 52 static void *sunxi_find_dtb(void) 53 { 54 uint64_t *u_boot_base; 55 int i; 56 57 u_boot_base = (void *)SUNXI_BL33_VIRT_BASE; 58 59 for (i = 0; i < 2048 / sizeof(uint64_t); i++) { 60 uint32_t *dtb_base; 61 62 if (u_boot_base[i] != PRELOADED_BL33_BASE) 63 continue; 64 65 /* Does the suspected U-Boot size look anyhow reasonable? */ 66 if (u_boot_base[i + 1] >= 256 * 1024 * 1024) 67 continue; 68 69 /* end of the image: base address + size */ 70 dtb_base = (void *)((char *)u_boot_base + u_boot_base[i + 1]); 71 72 if (fdt_check_header(dtb_base) != 0) 73 continue; 74 75 return dtb_base; 76 } 77 78 return NULL; 79 } 80 81 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 82 u_register_t arg2, u_register_t arg3) 83 { 84 /* Initialize the debug console as soon as possible */ 85 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ, 86 SUNXI_UART0_BAUDRATE, &console); 87 88 #ifdef BL32_BASE 89 /* Populate entry point information for BL32 */ 90 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 91 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 92 bl32_image_ep_info.pc = BL32_BASE; 93 #endif 94 95 /* Populate entry point information for BL33 */ 96 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 97 /* 98 * Tell BL31 where the non-trusted software image 99 * is located and the entry state information 100 */ 101 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 102 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 103 DISABLE_ALL_EXCEPTIONS); 104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 105 } 106 107 void bl31_plat_arch_setup(void) 108 { 109 sunxi_configure_mmu_el3(0); 110 } 111 112 void bl31_platform_setup(void) 113 { 114 const char *soc_name; 115 uint16_t soc_id = sunxi_read_soc_id(); 116 void *fdt; 117 118 switch (soc_id) { 119 case SUNXI_SOC_A64: 120 soc_name = "A64/H64/R18"; 121 break; 122 case SUNXI_SOC_H5: 123 soc_name = "H5"; 124 break; 125 case SUNXI_SOC_H6: 126 soc_name = "H6"; 127 break; 128 case SUNXI_SOC_H616: 129 soc_name = "H616"; 130 break; 131 default: 132 soc_name = "unknown"; 133 break; 134 } 135 NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id); 136 137 generic_delay_timer_init(); 138 139 fdt = sunxi_find_dtb(); 140 if (fdt) { 141 const char *model; 142 int length; 143 144 model = fdt_getprop(fdt, 0, "model", &length); 145 NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt, 146 model ?: "unknown"); 147 } else { 148 NOTICE("BL31: No DTB found.\n"); 149 } 150 151 /* Configure the interrupt controller */ 152 gicv2_driver_init(&sunxi_gic_data); 153 gicv2_distif_init(); 154 gicv2_pcpu_distif_init(); 155 gicv2_cpuif_enable(); 156 157 sunxi_security_setup(); 158 159 /* 160 * On the A64 U-Boot's SPL sets the bus clocks to some conservative 161 * values, to work around FEL mode instabilities with SRAM C accesses. 162 * FEL mode is gone when we reach ATF, so bring the AHB1 bus 163 * (the "main" bus) clock frequency back to the recommended 200MHz, 164 * for improved performance. 165 */ 166 if (soc_id == SUNXI_SOC_A64) 167 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180); 168 169 /* 170 * U-Boot or the kernel don't setup AHB2, which leaves it at the 171 * AHB1 frequency (200 MHz, see above). However Allwinner recommends 172 * 300 MHz, for improved Ethernet and USB performance. Switch the 173 * clock to use "PLL_PERIPH0 / 2". 174 */ 175 if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5) 176 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1); 177 178 sunxi_pmic_setup(soc_id, fdt); 179 180 sunxi_prepare_dtb(fdt); 181 182 INFO("BL31: Platform setup done\n"); 183 } 184 185 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 186 { 187 assert(sec_state_is_valid(type) != 0); 188 189 if (type == NON_SECURE) 190 return &bl33_image_ep_info; 191 192 if ((type == SECURE) && bl32_image_ep_info.pc) 193 return &bl32_image_ep_info; 194 195 return NULL; 196 } 197