1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <assert.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <generic_delay_timer.h> 12 #include <gicv2.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <sunxi_def.h> 16 #include <sunxi_mmap.h> 17 #include <uart_16550.h> 18 19 #include "sunxi_private.h" 20 21 static entry_point_info_t bl33_image_ep_info; 22 23 static console_16550_t console; 24 25 static const gicv2_driver_data_t sunxi_gic_data = { 26 .gicd_base = SUNXI_GICD_BASE, 27 .gicc_base = SUNXI_GICC_BASE, 28 }; 29 30 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 31 u_register_t arg2, u_register_t arg3) 32 { 33 /* Initialize the debug console as soon as possible */ 34 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ, 35 SUNXI_UART0_BAUDRATE, &console); 36 37 /* Populate entry point information for BL33 */ 38 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 39 /* 40 * Tell BL31 where the non-trusted software image 41 * is located and the entry state information 42 */ 43 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 44 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 45 DISABLE_ALL_EXCEPTIONS); 46 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 47 48 /* Turn off all secondary CPUs */ 49 sunxi_disable_secondary_cpus(plat_my_core_pos()); 50 } 51 52 void bl31_plat_arch_setup(void) 53 { 54 sunxi_configure_mmu_el3(0); 55 } 56 57 void bl31_platform_setup(void) 58 { 59 generic_delay_timer_init(); 60 61 /* Configure the interrupt controller */ 62 gicv2_driver_init(&sunxi_gic_data); 63 gicv2_distif_init(); 64 gicv2_pcpu_distif_init(); 65 gicv2_cpuif_enable(); 66 67 sunxi_security_setup(); 68 69 INFO("BL31: Platform setup done\n"); 70 } 71 72 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 73 { 74 assert(sec_state_is_valid(type) != 0); 75 assert(type == NON_SECURE); 76 77 return &bl33_image_ep_info; 78 } 79