1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <debug.h> 10 #include <errno.h> 11 #include <platform_def.h> 12 #include <types.h> 13 #include <utils_def.h> 14 #include <xlat_tables_arch_private.h> 15 #include <xlat_tables_defs.h> 16 #include <xlat_tables_v2.h> 17 18 #include "xlat_tables_private.h" 19 20 #if LOG_LEVEL < LOG_LEVEL_VERBOSE 21 22 void xlat_mmap_print(__unused mmap_region_t *const mmap) 23 { 24 /* Empty */ 25 } 26 27 void xlat_tables_print(__unused xlat_ctx_t *ctx) 28 { 29 /* Empty */ 30 } 31 32 #else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */ 33 34 void xlat_mmap_print(mmap_region_t *const mmap) 35 { 36 tf_printf("mmap:\n"); 37 const mmap_region_t *mm = mmap; 38 39 while (mm->size != 0U) { 40 tf_printf(" VA:0x%lx PA:0x%llx size:0x%zx attr:0x%x " 41 "granularity:0x%zx\n", mm->base_va, mm->base_pa, 42 mm->size, mm->attr, mm->granularity); 43 ++mm; 44 }; 45 tf_printf("\n"); 46 } 47 48 /* Print the attributes of the specified block descriptor. */ 49 static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc) 50 { 51 int mem_type_index = ATTR_INDEX_GET(desc); 52 int xlat_regime = ctx->xlat_regime; 53 54 if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) { 55 tf_printf("MEM"); 56 } else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) { 57 tf_printf("NC"); 58 } else { 59 assert(mem_type_index == ATTR_DEVICE_INDEX); 60 tf_printf("DEV"); 61 } 62 63 if (xlat_regime == EL3_REGIME) { 64 /* For EL3 only check the AP[2] and XN bits. */ 65 tf_printf((desc & LOWER_ATTRS(AP_RO)) ? "-RO" : "-RW"); 66 tf_printf((desc & UPPER_ATTRS(XN)) ? "-XN" : "-EXEC"); 67 } else { 68 assert(xlat_regime == EL1_EL0_REGIME); 69 /* 70 * For EL0 and EL1: 71 * - In AArch64 PXN and UXN can be set independently but in 72 * AArch32 there is no UXN (XN affects both privilege levels). 73 * For consistency, we set them simultaneously in both cases. 74 * - RO and RW permissions must be the same in EL1 and EL0. If 75 * EL0 can access that memory region, so can EL1, with the 76 * same permissions. 77 */ 78 #if ENABLE_ASSERTIONS 79 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME); 80 uint64_t xn_perm = desc & xn_mask; 81 82 assert((xn_perm == xn_mask) || (xn_perm == 0ULL)); 83 #endif 84 tf_printf((desc & LOWER_ATTRS(AP_RO)) ? "-RO" : "-RW"); 85 /* Only check one of PXN and UXN, the other one is the same. */ 86 tf_printf((desc & UPPER_ATTRS(PXN)) ? "-XN" : "-EXEC"); 87 /* 88 * Privileged regions can only be accessed from EL1, user 89 * regions can be accessed from EL1 and EL0. 90 */ 91 tf_printf((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) 92 ? "-USER" : "-PRIV"); 93 } 94 95 tf_printf(LOWER_ATTRS(NS) & desc ? "-NS" : "-S"); 96 } 97 98 static const char * const level_spacers[] = { 99 "[LV0] ", 100 " [LV1] ", 101 " [LV2] ", 102 " [LV3] " 103 }; 104 105 static const char *invalid_descriptors_ommited = 106 "%s(%d invalid descriptors omitted)\n"; 107 108 /* 109 * Recursive function that reads the translation tables passed as an argument 110 * and prints their status. 111 */ 112 static void xlat_tables_print_internal(xlat_ctx_t *ctx, 113 const uintptr_t table_base_va, 114 uint64_t *const table_base, const int table_entries, 115 const unsigned int level) 116 { 117 assert(level <= XLAT_TABLE_LEVEL_MAX); 118 119 uint64_t desc; 120 uintptr_t table_idx_va = table_base_va; 121 int table_idx = 0; 122 123 size_t level_size = XLAT_BLOCK_SIZE(level); 124 125 /* 126 * Keep track of how many invalid descriptors are counted in a row. 127 * Whenever multiple invalid descriptors are found, only the first one 128 * is printed, and a line is added to inform about how many descriptors 129 * have been omitted. 130 */ 131 int invalid_row_count = 0; 132 133 while (table_idx < table_entries) { 134 135 desc = table_base[table_idx]; 136 137 if ((desc & DESC_MASK) == INVALID_DESC) { 138 139 if (invalid_row_count == 0) { 140 tf_printf("%sVA:%p size:0x%zx\n", 141 level_spacers[level], 142 (void *)table_idx_va, level_size); 143 } 144 invalid_row_count++; 145 146 } else { 147 148 if (invalid_row_count > 1) { 149 tf_printf(invalid_descriptors_ommited, 150 level_spacers[level], 151 invalid_row_count - 1); 152 } 153 invalid_row_count = 0; 154 155 /* 156 * Check if this is a table or a block. Tables are only 157 * allowed in levels other than 3, but DESC_PAGE has the 158 * same value as DESC_TABLE, so we need to check. 159 */ 160 if (((desc & DESC_MASK) == TABLE_DESC) && 161 (level < XLAT_TABLE_LEVEL_MAX)) { 162 /* 163 * Do not print any PA for a table descriptor, 164 * as it doesn't directly map physical memory 165 * but instead points to the next translation 166 * table in the translation table walk. 167 */ 168 tf_printf("%sVA:%p size:0x%zx\n", 169 level_spacers[level], 170 (void *)table_idx_va, level_size); 171 172 uintptr_t addr_inner = desc & TABLE_ADDR_MASK; 173 174 xlat_tables_print_internal(ctx, table_idx_va, 175 (uint64_t *)addr_inner, 176 XLAT_TABLE_ENTRIES, level + 1); 177 } else { 178 tf_printf("%sVA:%p PA:0x%llx size:0x%zx ", 179 level_spacers[level], 180 (void *)table_idx_va, 181 (unsigned long long)(desc & TABLE_ADDR_MASK), 182 level_size); 183 xlat_desc_print(ctx, desc); 184 tf_printf("\n"); 185 } 186 } 187 188 table_idx++; 189 table_idx_va += level_size; 190 } 191 192 if (invalid_row_count > 1) { 193 tf_printf(invalid_descriptors_ommited, 194 level_spacers[level], invalid_row_count - 1); 195 } 196 } 197 198 void xlat_tables_print(xlat_ctx_t *ctx) 199 { 200 const char *xlat_regime_str; 201 if (ctx->xlat_regime == EL1_EL0_REGIME) { 202 xlat_regime_str = "1&0"; 203 } else { 204 assert(ctx->xlat_regime == EL3_REGIME); 205 xlat_regime_str = "3"; 206 } 207 VERBOSE("Translation tables state:\n"); 208 VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str); 209 VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address); 210 VERBOSE(" Max allowed VA: %p\n", (void *) ctx->va_max_address); 211 VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa); 212 VERBOSE(" Max mapped VA: %p\n", (void *) ctx->max_va); 213 214 VERBOSE(" Initial lookup level: %i\n", ctx->base_level); 215 VERBOSE(" Entries @initial lookup level: %i\n", 216 ctx->base_table_entries); 217 218 int used_page_tables; 219 #if PLAT_XLAT_TABLES_DYNAMIC 220 used_page_tables = 0; 221 for (unsigned int i = 0; i < ctx->tables_num; ++i) { 222 if (ctx->tables_mapped_regions[i] != 0) 223 ++used_page_tables; 224 } 225 #else 226 used_page_tables = ctx->next_table; 227 #endif 228 VERBOSE(" Used %i sub-tables out of %i (spare: %i)\n", 229 used_page_tables, ctx->tables_num, 230 ctx->tables_num - used_page_tables); 231 232 xlat_tables_print_internal(ctx, 0, ctx->base_table, 233 ctx->base_table_entries, ctx->base_level); 234 } 235 236 #endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */ 237 238 /* 239 * Do a translation table walk to find the block or page descriptor that maps 240 * virtual_addr. 241 * 242 * On success, return the address of the descriptor within the translation 243 * table. Its lookup level is stored in '*out_level'. 244 * On error, return NULL. 245 * 246 * xlat_table_base 247 * Base address for the initial lookup level. 248 * xlat_table_base_entries 249 * Number of entries in the translation table for the initial lookup level. 250 * virt_addr_space_size 251 * Size in bytes of the virtual address space. 252 */ 253 static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr, 254 void *xlat_table_base, 255 int xlat_table_base_entries, 256 unsigned long long virt_addr_space_size, 257 int *out_level) 258 { 259 unsigned int start_level; 260 uint64_t *table; 261 int entries; 262 263 start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size); 264 265 table = xlat_table_base; 266 entries = xlat_table_base_entries; 267 268 for (unsigned int level = start_level; 269 level <= XLAT_TABLE_LEVEL_MAX; 270 ++level) { 271 int idx; 272 uint64_t desc; 273 uint64_t desc_type; 274 275 idx = XLAT_TABLE_IDX(virtual_addr, level); 276 if (idx >= entries) { 277 WARN("Missing xlat table entry at address 0x%lx\n", 278 virtual_addr); 279 return NULL; 280 } 281 282 desc = table[idx]; 283 desc_type = desc & DESC_MASK; 284 285 if (desc_type == INVALID_DESC) { 286 VERBOSE("Invalid entry (memory not mapped)\n"); 287 return NULL; 288 } 289 290 if (level == XLAT_TABLE_LEVEL_MAX) { 291 /* 292 * Only page descriptors allowed at the final lookup 293 * level. 294 */ 295 assert(desc_type == PAGE_DESC); 296 *out_level = level; 297 return &table[idx]; 298 } 299 300 if (desc_type == BLOCK_DESC) { 301 *out_level = level; 302 return &table[idx]; 303 } 304 305 assert(desc_type == TABLE_DESC); 306 table = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK); 307 entries = XLAT_TABLE_ENTRIES; 308 } 309 310 /* 311 * This shouldn't be reached, the translation table walk should end at 312 * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop. 313 */ 314 assert(0); 315 316 return NULL; 317 } 318 319 320 static int get_mem_attributes_internal(const xlat_ctx_t *ctx, uintptr_t base_va, 321 uint32_t *attributes, uint64_t **table_entry, 322 unsigned long long *addr_pa, int *table_level) 323 { 324 uint64_t *entry; 325 uint64_t desc; 326 int level; 327 unsigned long long virt_addr_space_size; 328 329 /* 330 * Sanity-check arguments. 331 */ 332 assert(ctx != NULL); 333 assert(ctx->initialized); 334 assert(ctx->xlat_regime == EL1_EL0_REGIME || ctx->xlat_regime == EL3_REGIME); 335 336 virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1; 337 assert(virt_addr_space_size > 0); 338 339 entry = find_xlat_table_entry(base_va, 340 ctx->base_table, 341 ctx->base_table_entries, 342 virt_addr_space_size, 343 &level); 344 if (entry == NULL) { 345 WARN("Address %p is not mapped.\n", (void *)base_va); 346 return -EINVAL; 347 } 348 349 if (addr_pa != NULL) { 350 *addr_pa = *entry & TABLE_ADDR_MASK; 351 } 352 353 if (table_entry != NULL) { 354 *table_entry = entry; 355 } 356 357 if (table_level != NULL) { 358 *table_level = level; 359 } 360 361 desc = *entry; 362 363 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 364 VERBOSE("Attributes: "); 365 xlat_desc_print(ctx, desc); 366 tf_printf("\n"); 367 #endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */ 368 369 assert(attributes != NULL); 370 *attributes = 0; 371 372 int attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK; 373 374 if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) { 375 *attributes |= MT_MEMORY; 376 } else if (attr_index == ATTR_NON_CACHEABLE_INDEX) { 377 *attributes |= MT_NON_CACHEABLE; 378 } else { 379 assert(attr_index == ATTR_DEVICE_INDEX); 380 *attributes |= MT_DEVICE; 381 } 382 383 int ap2_bit = (desc >> AP2_SHIFT) & 1; 384 385 if (ap2_bit == AP2_RW) 386 *attributes |= MT_RW; 387 388 if (ctx->xlat_regime == EL1_EL0_REGIME) { 389 int ap1_bit = (desc >> AP1_SHIFT) & 1; 390 if (ap1_bit == AP1_ACCESS_UNPRIVILEGED) 391 *attributes |= MT_USER; 392 } 393 394 int ns_bit = (desc >> NS_SHIFT) & 1; 395 396 if (ns_bit == 1) 397 *attributes |= MT_NS; 398 399 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime); 400 401 if ((desc & xn_mask) == xn_mask) { 402 *attributes |= MT_EXECUTE_NEVER; 403 } else { 404 assert((desc & xn_mask) == 0); 405 } 406 407 return 0; 408 } 409 410 411 int get_mem_attributes(const xlat_ctx_t *ctx, uintptr_t base_va, 412 uint32_t *attributes) 413 { 414 return get_mem_attributes_internal(ctx, base_va, attributes, 415 NULL, NULL, NULL); 416 } 417 418 419 int change_mem_attributes(xlat_ctx_t *ctx, 420 uintptr_t base_va, 421 size_t size, 422 uint32_t attr) 423 { 424 /* Note: This implementation isn't optimized. */ 425 426 assert(ctx != NULL); 427 assert(ctx->initialized); 428 429 unsigned long long virt_addr_space_size = 430 (unsigned long long)ctx->va_max_address + 1; 431 assert(virt_addr_space_size > 0); 432 433 if (!IS_PAGE_ALIGNED(base_va)) { 434 WARN("%s: Address %p is not aligned on a page boundary.\n", 435 __func__, (void *)base_va); 436 return -EINVAL; 437 } 438 439 if (size == 0) { 440 WARN("%s: Size is 0.\n", __func__); 441 return -EINVAL; 442 } 443 444 if ((size % PAGE_SIZE) != 0) { 445 WARN("%s: Size 0x%zx is not a multiple of a page size.\n", 446 __func__, size); 447 return -EINVAL; 448 } 449 450 if (((attr & MT_EXECUTE_NEVER) == 0) && ((attr & MT_RW) != 0)) { 451 WARN("%s: Mapping memory as read-write and executable not allowed.\n", 452 __func__); 453 return -EINVAL; 454 } 455 456 int pages_count = size / PAGE_SIZE; 457 458 VERBOSE("Changing memory attributes of %i pages starting from address %p...\n", 459 pages_count, (void *)base_va); 460 461 uintptr_t base_va_original = base_va; 462 463 /* 464 * Sanity checks. 465 */ 466 for (int i = 0; i < pages_count; ++i) { 467 uint64_t *entry; 468 uint64_t desc; 469 int level; 470 471 entry = find_xlat_table_entry(base_va, 472 ctx->base_table, 473 ctx->base_table_entries, 474 virt_addr_space_size, 475 &level); 476 if (entry == NULL) { 477 WARN("Address %p is not mapped.\n", (void *)base_va); 478 return -EINVAL; 479 } 480 481 desc = *entry; 482 483 /* 484 * Check that all the required pages are mapped at page 485 * granularity. 486 */ 487 if (((desc & DESC_MASK) != PAGE_DESC) || 488 (level != XLAT_TABLE_LEVEL_MAX)) { 489 WARN("Address %p is not mapped at the right granularity.\n", 490 (void *)base_va); 491 WARN("Granularity is 0x%llx, should be 0x%x.\n", 492 (unsigned long long)XLAT_BLOCK_SIZE(level), PAGE_SIZE); 493 return -EINVAL; 494 } 495 496 /* 497 * If the region type is device, it shouldn't be executable. 498 */ 499 int attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK; 500 if (attr_index == ATTR_DEVICE_INDEX) { 501 if ((attr & MT_EXECUTE_NEVER) == 0) { 502 WARN("Setting device memory as executable at address %p.", 503 (void *)base_va); 504 return -EINVAL; 505 } 506 } 507 508 base_va += PAGE_SIZE; 509 } 510 511 /* Restore original value. */ 512 base_va = base_va_original; 513 514 for (int i = 0; i < pages_count; ++i) { 515 516 uint32_t old_attr, new_attr; 517 uint64_t *entry; 518 int level; 519 unsigned long long addr_pa; 520 521 get_mem_attributes_internal(ctx, base_va, &old_attr, 522 &entry, &addr_pa, &level); 523 524 /* 525 * From attr, only MT_RO/MT_RW, MT_EXECUTE/MT_EXECUTE_NEVER and 526 * MT_USER/MT_PRIVILEGED are taken into account. Any other 527 * information is ignored. 528 */ 529 530 /* Clean the old attributes so that they can be rebuilt. */ 531 new_attr = old_attr & ~(MT_RW | MT_EXECUTE_NEVER | MT_USER); 532 533 /* 534 * Update attributes, but filter out the ones this function 535 * isn't allowed to change. 536 */ 537 new_attr |= attr & (MT_RW | MT_EXECUTE_NEVER | MT_USER); 538 539 /* 540 * The break-before-make sequence requires writing an invalid 541 * descriptor and making sure that the system sees the change 542 * before writing the new descriptor. 543 */ 544 *entry = INVALID_DESC; 545 546 /* Invalidate any cached copy of this mapping in the TLBs. */ 547 xlat_arch_tlbi_va_regime(base_va, ctx->xlat_regime); 548 549 /* Ensure completion of the invalidation. */ 550 xlat_arch_tlbi_va_sync(); 551 552 /* Write new descriptor */ 553 *entry = xlat_desc(ctx, new_attr, addr_pa, level); 554 555 base_va += PAGE_SIZE; 556 } 557 558 /* Ensure that the last descriptor writen is seen by the system. */ 559 dsbish(); 560 561 return 0; 562 } 563