1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <platform.h> 12 #include <pmf.h> 13 #include <runtime_instr.h> 14 #include <smcc.h> 15 #include <string.h> 16 #include "psci_private.h" 17 18 /******************************************************************************* 19 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 20 ******************************************************************************/ 21 int psci_cpu_on(u_register_t target_cpu, 22 uintptr_t entrypoint, 23 u_register_t context_id) 24 25 { 26 int rc; 27 entry_point_info_t ep; 28 29 /* Determine if the cpu exists of not */ 30 rc = psci_validate_mpidr(target_cpu); 31 if (rc != PSCI_E_SUCCESS) 32 return PSCI_E_INVALID_PARAMS; 33 34 /* Validate the entry point and get the entry_point_info */ 35 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 36 if (rc != PSCI_E_SUCCESS) 37 return rc; 38 39 /* 40 * To turn this cpu on, specify which power 41 * levels need to be turned on 42 */ 43 return psci_cpu_on_start(target_cpu, &ep); 44 } 45 46 unsigned int psci_version(void) 47 { 48 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 49 } 50 51 int psci_cpu_suspend(unsigned int power_state, 52 uintptr_t entrypoint, 53 u_register_t context_id) 54 { 55 int rc; 56 unsigned int target_pwrlvl, is_power_down_state; 57 entry_point_info_t ep; 58 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 59 plat_local_state_t cpu_pd_state; 60 61 /* Validate the power_state parameter */ 62 rc = psci_validate_power_state(power_state, &state_info); 63 if (rc != PSCI_E_SUCCESS) { 64 assert(rc == PSCI_E_INVALID_PARAMS); 65 return rc; 66 } 67 68 /* 69 * Get the value of the state type bit from the power state parameter. 70 */ 71 is_power_down_state = psci_get_pstate_type(power_state); 72 73 /* Sanity check the requested suspend levels */ 74 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 75 == PSCI_E_SUCCESS); 76 77 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 78 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 79 ERROR("Invalid target power level for suspend operation\n"); 80 panic(); 81 } 82 83 /* Fast path for CPU standby.*/ 84 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 85 if (!psci_plat_pm_ops->cpu_standby) 86 return PSCI_E_INVALID_PARAMS; 87 88 /* 89 * Set the state of the CPU power domain to the platform 90 * specific retention state and enter the standby state. 91 */ 92 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 93 psci_set_cpu_local_state(cpu_pd_state); 94 95 #if ENABLE_PSCI_STAT 96 plat_psci_stat_accounting_start(&state_info); 97 #endif 98 99 #if ENABLE_RUNTIME_INSTRUMENTATION 100 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 101 RT_INSTR_ENTER_HW_LOW_PWR, 102 PMF_NO_CACHE_MAINT); 103 #endif 104 105 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 106 107 /* Upon exit from standby, set the state back to RUN. */ 108 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 109 110 #if ENABLE_RUNTIME_INSTRUMENTATION 111 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 112 RT_INSTR_EXIT_HW_LOW_PWR, 113 PMF_NO_CACHE_MAINT); 114 #endif 115 116 #if ENABLE_PSCI_STAT 117 plat_psci_stat_accounting_stop(&state_info); 118 119 /* Update PSCI stats */ 120 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); 121 #endif 122 123 return PSCI_E_SUCCESS; 124 } 125 126 /* 127 * If a power down state has been requested, we need to verify entry 128 * point and program entry information. 129 */ 130 if (is_power_down_state) { 131 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 132 if (rc != PSCI_E_SUCCESS) 133 return rc; 134 } 135 136 /* 137 * Do what is needed to enter the power down state. Upon success, 138 * enter the final wfi which will power down this CPU. This function 139 * might return if the power down was abandoned for any reason, e.g. 140 * arrival of an interrupt 141 */ 142 psci_cpu_suspend_start(&ep, 143 target_pwrlvl, 144 &state_info, 145 is_power_down_state); 146 147 return PSCI_E_SUCCESS; 148 } 149 150 151 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 152 { 153 int rc; 154 psci_power_state_t state_info; 155 entry_point_info_t ep; 156 157 /* Check if the current CPU is the last ON CPU in the system */ 158 if (!psci_is_last_on_cpu()) 159 return PSCI_E_DENIED; 160 161 /* Validate the entry point and get the entry_point_info */ 162 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 163 if (rc != PSCI_E_SUCCESS) 164 return rc; 165 166 /* Query the psci_power_state for system suspend */ 167 psci_query_sys_suspend_pwrstate(&state_info); 168 169 /* Ensure that the psci_power_state makes sense */ 170 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); 171 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 172 == PSCI_E_SUCCESS); 173 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); 174 175 /* 176 * Do what is needed to enter the system suspend state. This function 177 * might return if the power down was abandoned for any reason, e.g. 178 * arrival of an interrupt 179 */ 180 psci_cpu_suspend_start(&ep, 181 PLAT_MAX_PWR_LVL, 182 &state_info, 183 PSTATE_TYPE_POWERDOWN); 184 185 return PSCI_E_SUCCESS; 186 } 187 188 int psci_cpu_off(void) 189 { 190 int rc; 191 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 192 193 /* 194 * Do what is needed to power off this CPU and possible higher power 195 * levels if it able to do so. Upon success, enter the final wfi 196 * which will power down this CPU. 197 */ 198 rc = psci_do_cpu_off(target_pwrlvl); 199 200 /* 201 * The only error cpu_off can return is E_DENIED. So check if that's 202 * indeed the case. 203 */ 204 assert(rc == PSCI_E_DENIED); 205 206 return rc; 207 } 208 209 int psci_affinity_info(u_register_t target_affinity, 210 unsigned int lowest_affinity_level) 211 { 212 int target_idx; 213 214 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 215 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 216 return PSCI_E_INVALID_PARAMS; 217 218 /* Calculate the cpu index of the target */ 219 target_idx = plat_core_pos_by_mpidr(target_affinity); 220 if (target_idx == -1) 221 return PSCI_E_INVALID_PARAMS; 222 223 /* 224 * Generic management: 225 * Perform cache maintanence ahead of reading the target CPU state to 226 * ensure that the data is not stale. 227 * There is a theoretical edge case where the cache may contain stale 228 * data for the target CPU data - this can occur under the following 229 * conditions: 230 * - the target CPU is in another cluster from the current 231 * - the target CPU was the last CPU to shutdown on its cluster 232 * - the cluster was removed from coherency as part of the CPU shutdown 233 * 234 * In this case the cache maintenace that was performed as part of the 235 * target CPUs shutdown was not seen by the current CPU's cluster. And 236 * so the cache may contain stale data for the target CPU. 237 */ 238 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 239 240 return psci_get_aff_info_state_by_idx(target_idx); 241 } 242 243 int psci_migrate(u_register_t target_cpu) 244 { 245 int rc; 246 u_register_t resident_cpu_mpidr; 247 248 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 249 if (rc != PSCI_TOS_UP_MIG_CAP) 250 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 251 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 252 253 /* 254 * Migrate should only be invoked on the CPU where 255 * the Secure OS is resident. 256 */ 257 if (resident_cpu_mpidr != read_mpidr_el1()) 258 return PSCI_E_NOT_PRESENT; 259 260 /* Check the validity of the specified target cpu */ 261 rc = psci_validate_mpidr(target_cpu); 262 if (rc != PSCI_E_SUCCESS) 263 return PSCI_E_INVALID_PARAMS; 264 265 assert(psci_spd_pm && psci_spd_pm->svc_migrate); 266 267 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 268 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 269 270 return rc; 271 } 272 273 int psci_migrate_info_type(void) 274 { 275 u_register_t resident_cpu_mpidr; 276 277 return psci_spd_migrate_info(&resident_cpu_mpidr); 278 } 279 280 long psci_migrate_info_up_cpu(void) 281 { 282 u_register_t resident_cpu_mpidr; 283 int rc; 284 285 /* 286 * Return value of this depends upon what 287 * psci_spd_migrate_info() returns. 288 */ 289 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 290 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) 291 return PSCI_E_INVALID_PARAMS; 292 293 return resident_cpu_mpidr; 294 } 295 296 int psci_node_hw_state(u_register_t target_cpu, 297 unsigned int power_level) 298 { 299 int rc; 300 301 /* Validate target_cpu */ 302 rc = psci_validate_mpidr(target_cpu); 303 if (rc != PSCI_E_SUCCESS) 304 return PSCI_E_INVALID_PARAMS; 305 306 /* Validate power_level against PLAT_MAX_PWR_LVL */ 307 if (power_level > PLAT_MAX_PWR_LVL) 308 return PSCI_E_INVALID_PARAMS; 309 310 /* 311 * Dispatch this call to platform to query power controller, and pass on 312 * to the caller what it returns 313 */ 314 assert(psci_plat_pm_ops->get_node_hw_state); 315 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 316 assert((rc >= HW_ON && rc <= HW_STANDBY) || rc == PSCI_E_NOT_SUPPORTED 317 || rc == PSCI_E_INVALID_PARAMS); 318 return rc; 319 } 320 321 int psci_features(unsigned int psci_fid) 322 { 323 unsigned int local_caps = psci_caps; 324 325 /* Check if it is a 64 bit function */ 326 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 327 local_caps &= PSCI_CAP_64BIT_MASK; 328 329 /* Check for invalid fid */ 330 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 331 && is_psci_fid(psci_fid))) 332 return PSCI_E_NOT_SUPPORTED; 333 334 335 /* Check if the psci fid is supported or not */ 336 if (!(local_caps & define_psci_cap(psci_fid))) 337 return PSCI_E_NOT_SUPPORTED; 338 339 /* Format the feature flags */ 340 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || 341 psci_fid == PSCI_CPU_SUSPEND_AARCH64) { 342 /* 343 * The trusted firmware does not support OS Initiated Mode. 344 */ 345 return (FF_PSTATE << FF_PSTATE_SHIFT) | 346 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); 347 } 348 349 /* Return 0 for all other fid's */ 350 return PSCI_E_SUCCESS; 351 } 352 353 /******************************************************************************* 354 * PSCI top level handler for servicing SMCs. 355 ******************************************************************************/ 356 u_register_t psci_smc_handler(uint32_t smc_fid, 357 u_register_t x1, 358 u_register_t x2, 359 u_register_t x3, 360 u_register_t x4, 361 void *cookie, 362 void *handle, 363 u_register_t flags) 364 { 365 if (is_caller_secure(flags)) 366 return SMC_UNK; 367 368 /* Check the fid against the capabilities */ 369 if (!(psci_caps & define_psci_cap(smc_fid))) 370 return SMC_UNK; 371 372 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 373 /* 32-bit PSCI function, clear top parameter bits */ 374 375 x1 = (uint32_t)x1; 376 x2 = (uint32_t)x2; 377 x3 = (uint32_t)x3; 378 379 switch (smc_fid) { 380 case PSCI_VERSION: 381 return psci_version(); 382 383 case PSCI_CPU_OFF: 384 return psci_cpu_off(); 385 386 case PSCI_CPU_SUSPEND_AARCH32: 387 return psci_cpu_suspend(x1, x2, x3); 388 389 case PSCI_CPU_ON_AARCH32: 390 return psci_cpu_on(x1, x2, x3); 391 392 case PSCI_AFFINITY_INFO_AARCH32: 393 return psci_affinity_info(x1, x2); 394 395 case PSCI_MIG_AARCH32: 396 return psci_migrate(x1); 397 398 case PSCI_MIG_INFO_TYPE: 399 return psci_migrate_info_type(); 400 401 case PSCI_MIG_INFO_UP_CPU_AARCH32: 402 return psci_migrate_info_up_cpu(); 403 404 case PSCI_NODE_HW_STATE_AARCH32: 405 return psci_node_hw_state(x1, x2); 406 407 case PSCI_SYSTEM_SUSPEND_AARCH32: 408 return psci_system_suspend(x1, x2); 409 410 case PSCI_SYSTEM_OFF: 411 psci_system_off(); 412 /* We should never return from psci_system_off() */ 413 414 case PSCI_SYSTEM_RESET: 415 psci_system_reset(); 416 /* We should never return from psci_system_reset() */ 417 418 case PSCI_FEATURES: 419 return psci_features(x1); 420 421 #if ENABLE_PSCI_STAT 422 case PSCI_STAT_RESIDENCY_AARCH32: 423 return psci_stat_residency(x1, x2); 424 425 case PSCI_STAT_COUNT_AARCH32: 426 return psci_stat_count(x1, x2); 427 #endif 428 case PSCI_MEM_PROTECT: 429 return psci_mem_protect(x1); 430 431 case PSCI_MEM_CHK_RANGE_AARCH32: 432 return psci_mem_chk_range(x1, x2); 433 434 case PSCI_SYSTEM_RESET2_AARCH32: 435 /* We should never return from psci_system_reset2() */ 436 return psci_system_reset2(x1, x2); 437 438 default: 439 break; 440 } 441 } else { 442 /* 64-bit PSCI function */ 443 444 switch (smc_fid) { 445 case PSCI_CPU_SUSPEND_AARCH64: 446 return psci_cpu_suspend(x1, x2, x3); 447 448 case PSCI_CPU_ON_AARCH64: 449 return psci_cpu_on(x1, x2, x3); 450 451 case PSCI_AFFINITY_INFO_AARCH64: 452 return psci_affinity_info(x1, x2); 453 454 case PSCI_MIG_AARCH64: 455 return psci_migrate(x1); 456 457 case PSCI_MIG_INFO_UP_CPU_AARCH64: 458 return psci_migrate_info_up_cpu(); 459 460 case PSCI_NODE_HW_STATE_AARCH64: 461 return psci_node_hw_state(x1, x2); 462 463 case PSCI_SYSTEM_SUSPEND_AARCH64: 464 return psci_system_suspend(x1, x2); 465 466 #if ENABLE_PSCI_STAT 467 case PSCI_STAT_RESIDENCY_AARCH64: 468 return psci_stat_residency(x1, x2); 469 470 case PSCI_STAT_COUNT_AARCH64: 471 return psci_stat_count(x1, x2); 472 #endif 473 474 case PSCI_MEM_CHK_RANGE_AARCH64: 475 return psci_mem_chk_range(x1, x2); 476 477 case PSCI_SYSTEM_RESET2_AARCH64: 478 /* We should never return from psci_system_reset2() */ 479 return psci_system_reset2(x1, x2); 480 481 default: 482 break; 483 } 484 } 485 486 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); 487 return SMC_UNK; 488 } 489