1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/pmf/pmf.h> 14 #include <lib/runtime_instr.h> 15 #include <lib/smccc.h> 16 #include <plat/common/platform.h> 17 #include <services/arm_arch_svc.h> 18 19 #include "psci_private.h" 20 21 /******************************************************************************* 22 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 23 ******************************************************************************/ 24 int psci_cpu_on(u_register_t target_cpu, 25 uintptr_t entrypoint, 26 u_register_t context_id) 27 28 { 29 int rc; 30 entry_point_info_t ep; 31 32 /* Determine if the cpu exists of not */ 33 rc = psci_validate_mpidr(target_cpu); 34 if (rc != PSCI_E_SUCCESS) 35 return PSCI_E_INVALID_PARAMS; 36 37 /* Validate the entry point and get the entry_point_info */ 38 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 39 if (rc != PSCI_E_SUCCESS) 40 return rc; 41 42 /* 43 * To turn this cpu on, specify which power 44 * levels need to be turned on 45 */ 46 return psci_cpu_on_start(target_cpu, &ep); 47 } 48 49 unsigned int psci_version(void) 50 { 51 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 52 } 53 54 int psci_cpu_suspend(unsigned int power_state, 55 uintptr_t entrypoint, 56 u_register_t context_id) 57 { 58 int rc; 59 unsigned int target_pwrlvl, is_power_down_state; 60 entry_point_info_t ep; 61 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 62 plat_local_state_t cpu_pd_state; 63 64 /* Validate the power_state parameter */ 65 rc = psci_validate_power_state(power_state, &state_info); 66 if (rc != PSCI_E_SUCCESS) { 67 assert(rc == PSCI_E_INVALID_PARAMS); 68 return rc; 69 } 70 71 /* 72 * Get the value of the state type bit from the power state parameter. 73 */ 74 is_power_down_state = psci_get_pstate_type(power_state); 75 76 /* Sanity check the requested suspend levels */ 77 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 78 == PSCI_E_SUCCESS); 79 80 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 81 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 82 ERROR("Invalid target power level for suspend operation\n"); 83 panic(); 84 } 85 86 /* Fast path for CPU standby.*/ 87 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 88 if (psci_plat_pm_ops->cpu_standby == NULL) 89 return PSCI_E_INVALID_PARAMS; 90 91 /* 92 * Set the state of the CPU power domain to the platform 93 * specific retention state and enter the standby state. 94 */ 95 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 96 psci_set_cpu_local_state(cpu_pd_state); 97 98 #if ENABLE_PSCI_STAT 99 plat_psci_stat_accounting_start(&state_info); 100 #endif 101 102 #if ENABLE_RUNTIME_INSTRUMENTATION 103 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 104 RT_INSTR_ENTER_HW_LOW_PWR, 105 PMF_NO_CACHE_MAINT); 106 #endif 107 108 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 109 110 /* Upon exit from standby, set the state back to RUN. */ 111 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 112 113 #if ENABLE_RUNTIME_INSTRUMENTATION 114 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 115 RT_INSTR_EXIT_HW_LOW_PWR, 116 PMF_NO_CACHE_MAINT); 117 #endif 118 119 #if ENABLE_PSCI_STAT 120 plat_psci_stat_accounting_stop(&state_info); 121 122 /* Update PSCI stats */ 123 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); 124 #endif 125 126 return PSCI_E_SUCCESS; 127 } 128 129 /* 130 * If a power down state has been requested, we need to verify entry 131 * point and program entry information. 132 */ 133 if (is_power_down_state != 0U) { 134 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 135 if (rc != PSCI_E_SUCCESS) 136 return rc; 137 } 138 139 /* 140 * Do what is needed to enter the power down state. Upon success, 141 * enter the final wfi which will power down this CPU. This function 142 * might return if the power down was abandoned for any reason, e.g. 143 * arrival of an interrupt 144 */ 145 psci_cpu_suspend_start(&ep, 146 target_pwrlvl, 147 &state_info, 148 is_power_down_state); 149 150 return PSCI_E_SUCCESS; 151 } 152 153 154 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 155 { 156 int rc; 157 psci_power_state_t state_info; 158 entry_point_info_t ep; 159 160 /* Check if the current CPU is the last ON CPU in the system */ 161 if (!psci_is_last_on_cpu()) 162 return PSCI_E_DENIED; 163 164 /* Validate the entry point and get the entry_point_info */ 165 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 166 if (rc != PSCI_E_SUCCESS) 167 return rc; 168 169 /* Query the psci_power_state for system suspend */ 170 psci_query_sys_suspend_pwrstate(&state_info); 171 172 /* 173 * Check if platform allows suspend to Highest power level 174 * (System level) 175 */ 176 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) 177 return PSCI_E_DENIED; 178 179 /* Ensure that the psci_power_state makes sense */ 180 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 181 == PSCI_E_SUCCESS); 182 assert(is_local_state_off( 183 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); 184 185 /* 186 * Do what is needed to enter the system suspend state. This function 187 * might return if the power down was abandoned for any reason, e.g. 188 * arrival of an interrupt 189 */ 190 psci_cpu_suspend_start(&ep, 191 PLAT_MAX_PWR_LVL, 192 &state_info, 193 PSTATE_TYPE_POWERDOWN); 194 195 return PSCI_E_SUCCESS; 196 } 197 198 int psci_cpu_off(void) 199 { 200 int rc; 201 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 202 203 /* 204 * Do what is needed to power off this CPU and possible higher power 205 * levels if it able to do so. Upon success, enter the final wfi 206 * which will power down this CPU. 207 */ 208 rc = psci_do_cpu_off(target_pwrlvl); 209 210 /* 211 * The only error cpu_off can return is E_DENIED. So check if that's 212 * indeed the case. 213 */ 214 assert(rc == PSCI_E_DENIED); 215 216 return rc; 217 } 218 219 int psci_affinity_info(u_register_t target_affinity, 220 unsigned int lowest_affinity_level) 221 { 222 int ret; 223 unsigned int target_idx; 224 225 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 226 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 227 return PSCI_E_INVALID_PARAMS; 228 229 /* Calculate the cpu index of the target */ 230 ret = plat_core_pos_by_mpidr(target_affinity); 231 if (ret == -1) { 232 return PSCI_E_INVALID_PARAMS; 233 } 234 target_idx = (unsigned int)ret; 235 236 /* 237 * Generic management: 238 * Perform cache maintanence ahead of reading the target CPU state to 239 * ensure that the data is not stale. 240 * There is a theoretical edge case where the cache may contain stale 241 * data for the target CPU data - this can occur under the following 242 * conditions: 243 * - the target CPU is in another cluster from the current 244 * - the target CPU was the last CPU to shutdown on its cluster 245 * - the cluster was removed from coherency as part of the CPU shutdown 246 * 247 * In this case the cache maintenace that was performed as part of the 248 * target CPUs shutdown was not seen by the current CPU's cluster. And 249 * so the cache may contain stale data for the target CPU. 250 */ 251 flush_cpu_data_by_index(target_idx, 252 psci_svc_cpu_data.aff_info_state); 253 254 return psci_get_aff_info_state_by_idx(target_idx); 255 } 256 257 int psci_migrate(u_register_t target_cpu) 258 { 259 int rc; 260 u_register_t resident_cpu_mpidr; 261 262 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 263 if (rc != PSCI_TOS_UP_MIG_CAP) 264 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 265 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 266 267 /* 268 * Migrate should only be invoked on the CPU where 269 * the Secure OS is resident. 270 */ 271 if (resident_cpu_mpidr != read_mpidr_el1()) 272 return PSCI_E_NOT_PRESENT; 273 274 /* Check the validity of the specified target cpu */ 275 rc = psci_validate_mpidr(target_cpu); 276 if (rc != PSCI_E_SUCCESS) 277 return PSCI_E_INVALID_PARAMS; 278 279 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); 280 281 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 282 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 283 284 return rc; 285 } 286 287 int psci_migrate_info_type(void) 288 { 289 u_register_t resident_cpu_mpidr; 290 291 return psci_spd_migrate_info(&resident_cpu_mpidr); 292 } 293 294 u_register_t psci_migrate_info_up_cpu(void) 295 { 296 u_register_t resident_cpu_mpidr; 297 int rc; 298 299 /* 300 * Return value of this depends upon what 301 * psci_spd_migrate_info() returns. 302 */ 303 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 304 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP)) 305 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS; 306 307 return resident_cpu_mpidr; 308 } 309 310 int psci_node_hw_state(u_register_t target_cpu, 311 unsigned int power_level) 312 { 313 int rc; 314 315 /* Validate target_cpu */ 316 rc = psci_validate_mpidr(target_cpu); 317 if (rc != PSCI_E_SUCCESS) 318 return PSCI_E_INVALID_PARAMS; 319 320 /* Validate power_level against PLAT_MAX_PWR_LVL */ 321 if (power_level > PLAT_MAX_PWR_LVL) 322 return PSCI_E_INVALID_PARAMS; 323 324 /* 325 * Dispatch this call to platform to query power controller, and pass on 326 * to the caller what it returns 327 */ 328 assert(psci_plat_pm_ops->get_node_hw_state != NULL); 329 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 330 assert(((rc >= HW_ON) && (rc <= HW_STANDBY)) 331 || (rc == PSCI_E_NOT_SUPPORTED) 332 || (rc == PSCI_E_INVALID_PARAMS)); 333 return rc; 334 } 335 336 int psci_features(unsigned int psci_fid) 337 { 338 unsigned int local_caps = psci_caps; 339 340 if (psci_fid == SMCCC_VERSION) 341 return PSCI_E_SUCCESS; 342 343 /* Check if it is a 64 bit function */ 344 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 345 local_caps &= PSCI_CAP_64BIT_MASK; 346 347 /* Check for invalid fid */ 348 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 349 && is_psci_fid(psci_fid))) 350 return PSCI_E_NOT_SUPPORTED; 351 352 353 /* Check if the psci fid is supported or not */ 354 if ((local_caps & define_psci_cap(psci_fid)) == 0U) 355 return PSCI_E_NOT_SUPPORTED; 356 357 /* Format the feature flags */ 358 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) || 359 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) { 360 /* 361 * The trusted firmware does not support OS Initiated Mode. 362 */ 363 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) | 364 (((FF_SUPPORTS_OS_INIT_MODE == 1U) ? 0U : 1U) 365 << FF_MODE_SUPPORT_SHIFT)); 366 return (int) ret; 367 } 368 369 /* Return 0 for all other fid's */ 370 return PSCI_E_SUCCESS; 371 } 372 373 /******************************************************************************* 374 * PSCI top level handler for servicing SMCs. 375 ******************************************************************************/ 376 u_register_t psci_smc_handler(uint32_t smc_fid, 377 u_register_t x1, 378 u_register_t x2, 379 u_register_t x3, 380 u_register_t x4, 381 void *cookie, 382 void *handle, 383 u_register_t flags) 384 { 385 u_register_t ret; 386 387 if (is_caller_secure(flags)) 388 return (u_register_t)SMC_UNK; 389 390 /* Check the fid against the capabilities */ 391 if ((psci_caps & define_psci_cap(smc_fid)) == 0U) 392 return (u_register_t)SMC_UNK; 393 394 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 395 /* 32-bit PSCI function, clear top parameter bits */ 396 397 uint32_t r1 = (uint32_t)x1; 398 uint32_t r2 = (uint32_t)x2; 399 uint32_t r3 = (uint32_t)x3; 400 401 switch (smc_fid) { 402 case PSCI_VERSION: 403 ret = (u_register_t)psci_version(); 404 break; 405 406 case PSCI_CPU_OFF: 407 ret = (u_register_t)psci_cpu_off(); 408 break; 409 410 case PSCI_CPU_SUSPEND_AARCH32: 411 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3); 412 break; 413 414 case PSCI_CPU_ON_AARCH32: 415 ret = (u_register_t)psci_cpu_on(r1, r2, r3); 416 break; 417 418 case PSCI_AFFINITY_INFO_AARCH32: 419 ret = (u_register_t)psci_affinity_info(r1, r2); 420 break; 421 422 case PSCI_MIG_AARCH32: 423 ret = (u_register_t)psci_migrate(r1); 424 break; 425 426 case PSCI_MIG_INFO_TYPE: 427 ret = (u_register_t)psci_migrate_info_type(); 428 break; 429 430 case PSCI_MIG_INFO_UP_CPU_AARCH32: 431 ret = psci_migrate_info_up_cpu(); 432 break; 433 434 case PSCI_NODE_HW_STATE_AARCH32: 435 ret = (u_register_t)psci_node_hw_state(r1, r2); 436 break; 437 438 case PSCI_SYSTEM_SUSPEND_AARCH32: 439 ret = (u_register_t)psci_system_suspend(r1, r2); 440 break; 441 442 case PSCI_SYSTEM_OFF: 443 psci_system_off(); 444 /* We should never return from psci_system_off() */ 445 break; 446 447 case PSCI_SYSTEM_RESET: 448 psci_system_reset(); 449 /* We should never return from psci_system_reset() */ 450 break; 451 452 case PSCI_FEATURES: 453 ret = (u_register_t)psci_features(r1); 454 break; 455 456 #if ENABLE_PSCI_STAT 457 case PSCI_STAT_RESIDENCY_AARCH32: 458 ret = psci_stat_residency(r1, r2); 459 break; 460 461 case PSCI_STAT_COUNT_AARCH32: 462 ret = psci_stat_count(r1, r2); 463 break; 464 #endif 465 case PSCI_MEM_PROTECT: 466 ret = psci_mem_protect(r1); 467 break; 468 469 case PSCI_MEM_CHK_RANGE_AARCH32: 470 ret = psci_mem_chk_range(r1, r2); 471 break; 472 473 case PSCI_SYSTEM_RESET2_AARCH32: 474 /* We should never return from psci_system_reset2() */ 475 ret = psci_system_reset2(r1, r2); 476 break; 477 478 default: 479 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 480 ret = (u_register_t)SMC_UNK; 481 break; 482 } 483 } else { 484 /* 64-bit PSCI function */ 485 486 switch (smc_fid) { 487 case PSCI_CPU_SUSPEND_AARCH64: 488 ret = (u_register_t) 489 psci_cpu_suspend((unsigned int)x1, x2, x3); 490 break; 491 492 case PSCI_CPU_ON_AARCH64: 493 ret = (u_register_t)psci_cpu_on(x1, x2, x3); 494 break; 495 496 case PSCI_AFFINITY_INFO_AARCH64: 497 ret = (u_register_t) 498 psci_affinity_info(x1, (unsigned int)x2); 499 break; 500 501 case PSCI_MIG_AARCH64: 502 ret = (u_register_t)psci_migrate(x1); 503 break; 504 505 case PSCI_MIG_INFO_UP_CPU_AARCH64: 506 ret = psci_migrate_info_up_cpu(); 507 break; 508 509 case PSCI_NODE_HW_STATE_AARCH64: 510 ret = (u_register_t)psci_node_hw_state( 511 x1, (unsigned int) x2); 512 break; 513 514 case PSCI_SYSTEM_SUSPEND_AARCH64: 515 ret = (u_register_t)psci_system_suspend(x1, x2); 516 break; 517 518 #if ENABLE_PSCI_STAT 519 case PSCI_STAT_RESIDENCY_AARCH64: 520 ret = psci_stat_residency(x1, (unsigned int) x2); 521 break; 522 523 case PSCI_STAT_COUNT_AARCH64: 524 ret = psci_stat_count(x1, (unsigned int) x2); 525 break; 526 #endif 527 528 case PSCI_MEM_CHK_RANGE_AARCH64: 529 ret = psci_mem_chk_range(x1, x2); 530 break; 531 532 case PSCI_SYSTEM_RESET2_AARCH64: 533 /* We should never return from psci_system_reset2() */ 534 ret = psci_system_reset2((uint32_t) x1, x2); 535 break; 536 537 default: 538 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 539 ret = (u_register_t)SMC_UNK; 540 break; 541 } 542 } 543 544 return ret; 545 } 546