1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_arch_svc.h> 10 #include <assert.h> 11 #include <debug.h> 12 #include <platform.h> 13 #include <pmf.h> 14 #include <runtime_instr.h> 15 #include <smcc.h> 16 #include <string.h> 17 #include "psci_private.h" 18 19 /******************************************************************************* 20 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 21 ******************************************************************************/ 22 int psci_cpu_on(u_register_t target_cpu, 23 uintptr_t entrypoint, 24 u_register_t context_id) 25 26 { 27 int rc; 28 entry_point_info_t ep; 29 30 /* Determine if the cpu exists of not */ 31 rc = psci_validate_mpidr(target_cpu); 32 if (rc != PSCI_E_SUCCESS) 33 return PSCI_E_INVALID_PARAMS; 34 35 /* Validate the entry point and get the entry_point_info */ 36 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 37 if (rc != PSCI_E_SUCCESS) 38 return rc; 39 40 /* 41 * To turn this cpu on, specify which power 42 * levels need to be turned on 43 */ 44 return psci_cpu_on_start(target_cpu, &ep); 45 } 46 47 unsigned int psci_version(void) 48 { 49 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 50 } 51 52 int psci_cpu_suspend(unsigned int power_state, 53 uintptr_t entrypoint, 54 u_register_t context_id) 55 { 56 int rc; 57 unsigned int target_pwrlvl, is_power_down_state; 58 entry_point_info_t ep; 59 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 60 plat_local_state_t cpu_pd_state; 61 62 /* Validate the power_state parameter */ 63 rc = psci_validate_power_state(power_state, &state_info); 64 if (rc != PSCI_E_SUCCESS) { 65 assert(rc == PSCI_E_INVALID_PARAMS); 66 return rc; 67 } 68 69 /* 70 * Get the value of the state type bit from the power state parameter. 71 */ 72 is_power_down_state = psci_get_pstate_type(power_state); 73 74 /* Sanity check the requested suspend levels */ 75 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 76 == PSCI_E_SUCCESS); 77 78 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 79 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 80 ERROR("Invalid target power level for suspend operation\n"); 81 panic(); 82 } 83 84 /* Fast path for CPU standby.*/ 85 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 86 if (!psci_plat_pm_ops->cpu_standby) 87 return PSCI_E_INVALID_PARAMS; 88 89 /* 90 * Set the state of the CPU power domain to the platform 91 * specific retention state and enter the standby state. 92 */ 93 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 94 psci_set_cpu_local_state(cpu_pd_state); 95 96 #if ENABLE_PSCI_STAT 97 plat_psci_stat_accounting_start(&state_info); 98 #endif 99 100 #if ENABLE_RUNTIME_INSTRUMENTATION 101 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 102 RT_INSTR_ENTER_HW_LOW_PWR, 103 PMF_NO_CACHE_MAINT); 104 #endif 105 106 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 107 108 /* Upon exit from standby, set the state back to RUN. */ 109 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 110 111 #if ENABLE_RUNTIME_INSTRUMENTATION 112 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 113 RT_INSTR_EXIT_HW_LOW_PWR, 114 PMF_NO_CACHE_MAINT); 115 #endif 116 117 #if ENABLE_PSCI_STAT 118 plat_psci_stat_accounting_stop(&state_info); 119 120 /* Update PSCI stats */ 121 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); 122 #endif 123 124 return PSCI_E_SUCCESS; 125 } 126 127 /* 128 * If a power down state has been requested, we need to verify entry 129 * point and program entry information. 130 */ 131 if (is_power_down_state) { 132 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 133 if (rc != PSCI_E_SUCCESS) 134 return rc; 135 } 136 137 /* 138 * Do what is needed to enter the power down state. Upon success, 139 * enter the final wfi which will power down this CPU. This function 140 * might return if the power down was abandoned for any reason, e.g. 141 * arrival of an interrupt 142 */ 143 psci_cpu_suspend_start(&ep, 144 target_pwrlvl, 145 &state_info, 146 is_power_down_state); 147 148 return PSCI_E_SUCCESS; 149 } 150 151 152 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 153 { 154 int rc; 155 psci_power_state_t state_info; 156 entry_point_info_t ep; 157 158 /* Check if the current CPU is the last ON CPU in the system */ 159 if (!psci_is_last_on_cpu()) 160 return PSCI_E_DENIED; 161 162 /* Validate the entry point and get the entry_point_info */ 163 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 164 if (rc != PSCI_E_SUCCESS) 165 return rc; 166 167 /* Query the psci_power_state for system suspend */ 168 psci_query_sys_suspend_pwrstate(&state_info); 169 170 /* Ensure that the psci_power_state makes sense */ 171 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); 172 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 173 == PSCI_E_SUCCESS); 174 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); 175 176 /* 177 * Do what is needed to enter the system suspend state. This function 178 * might return if the power down was abandoned for any reason, e.g. 179 * arrival of an interrupt 180 */ 181 psci_cpu_suspend_start(&ep, 182 PLAT_MAX_PWR_LVL, 183 &state_info, 184 PSTATE_TYPE_POWERDOWN); 185 186 return PSCI_E_SUCCESS; 187 } 188 189 int psci_cpu_off(void) 190 { 191 int rc; 192 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 193 194 /* 195 * Do what is needed to power off this CPU and possible higher power 196 * levels if it able to do so. Upon success, enter the final wfi 197 * which will power down this CPU. 198 */ 199 rc = psci_do_cpu_off(target_pwrlvl); 200 201 /* 202 * The only error cpu_off can return is E_DENIED. So check if that's 203 * indeed the case. 204 */ 205 assert(rc == PSCI_E_DENIED); 206 207 return rc; 208 } 209 210 int psci_affinity_info(u_register_t target_affinity, 211 unsigned int lowest_affinity_level) 212 { 213 int target_idx; 214 215 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 216 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 217 return PSCI_E_INVALID_PARAMS; 218 219 /* Calculate the cpu index of the target */ 220 target_idx = plat_core_pos_by_mpidr(target_affinity); 221 if (target_idx == -1) 222 return PSCI_E_INVALID_PARAMS; 223 224 /* 225 * Generic management: 226 * Perform cache maintanence ahead of reading the target CPU state to 227 * ensure that the data is not stale. 228 * There is a theoretical edge case where the cache may contain stale 229 * data for the target CPU data - this can occur under the following 230 * conditions: 231 * - the target CPU is in another cluster from the current 232 * - the target CPU was the last CPU to shutdown on its cluster 233 * - the cluster was removed from coherency as part of the CPU shutdown 234 * 235 * In this case the cache maintenace that was performed as part of the 236 * target CPUs shutdown was not seen by the current CPU's cluster. And 237 * so the cache may contain stale data for the target CPU. 238 */ 239 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 240 241 return psci_get_aff_info_state_by_idx(target_idx); 242 } 243 244 int psci_migrate(u_register_t target_cpu) 245 { 246 int rc; 247 u_register_t resident_cpu_mpidr; 248 249 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 250 if (rc != PSCI_TOS_UP_MIG_CAP) 251 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 252 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 253 254 /* 255 * Migrate should only be invoked on the CPU where 256 * the Secure OS is resident. 257 */ 258 if (resident_cpu_mpidr != read_mpidr_el1()) 259 return PSCI_E_NOT_PRESENT; 260 261 /* Check the validity of the specified target cpu */ 262 rc = psci_validate_mpidr(target_cpu); 263 if (rc != PSCI_E_SUCCESS) 264 return PSCI_E_INVALID_PARAMS; 265 266 assert(psci_spd_pm && psci_spd_pm->svc_migrate); 267 268 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 269 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 270 271 return rc; 272 } 273 274 int psci_migrate_info_type(void) 275 { 276 u_register_t resident_cpu_mpidr; 277 278 return psci_spd_migrate_info(&resident_cpu_mpidr); 279 } 280 281 long psci_migrate_info_up_cpu(void) 282 { 283 u_register_t resident_cpu_mpidr; 284 int rc; 285 286 /* 287 * Return value of this depends upon what 288 * psci_spd_migrate_info() returns. 289 */ 290 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 291 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) 292 return PSCI_E_INVALID_PARAMS; 293 294 return resident_cpu_mpidr; 295 } 296 297 int psci_node_hw_state(u_register_t target_cpu, 298 unsigned int power_level) 299 { 300 int rc; 301 302 /* Validate target_cpu */ 303 rc = psci_validate_mpidr(target_cpu); 304 if (rc != PSCI_E_SUCCESS) 305 return PSCI_E_INVALID_PARAMS; 306 307 /* Validate power_level against PLAT_MAX_PWR_LVL */ 308 if (power_level > PLAT_MAX_PWR_LVL) 309 return PSCI_E_INVALID_PARAMS; 310 311 /* 312 * Dispatch this call to platform to query power controller, and pass on 313 * to the caller what it returns 314 */ 315 assert(psci_plat_pm_ops->get_node_hw_state); 316 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 317 assert((rc >= HW_ON && rc <= HW_STANDBY) || rc == PSCI_E_NOT_SUPPORTED 318 || rc == PSCI_E_INVALID_PARAMS); 319 return rc; 320 } 321 322 int psci_features(unsigned int psci_fid) 323 { 324 unsigned int local_caps = psci_caps; 325 326 if (psci_fid == SMCCC_VERSION) 327 return PSCI_E_SUCCESS; 328 329 /* Check if it is a 64 bit function */ 330 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 331 local_caps &= PSCI_CAP_64BIT_MASK; 332 333 /* Check for invalid fid */ 334 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 335 && is_psci_fid(psci_fid))) 336 return PSCI_E_NOT_SUPPORTED; 337 338 339 /* Check if the psci fid is supported or not */ 340 if (!(local_caps & define_psci_cap(psci_fid))) 341 return PSCI_E_NOT_SUPPORTED; 342 343 /* Format the feature flags */ 344 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || 345 psci_fid == PSCI_CPU_SUSPEND_AARCH64) { 346 /* 347 * The trusted firmware does not support OS Initiated Mode. 348 */ 349 return (FF_PSTATE << FF_PSTATE_SHIFT) | 350 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); 351 } 352 353 /* Return 0 for all other fid's */ 354 return PSCI_E_SUCCESS; 355 } 356 357 /******************************************************************************* 358 * PSCI top level handler for servicing SMCs. 359 ******************************************************************************/ 360 u_register_t psci_smc_handler(uint32_t smc_fid, 361 u_register_t x1, 362 u_register_t x2, 363 u_register_t x3, 364 u_register_t x4, 365 void *cookie, 366 void *handle, 367 u_register_t flags) 368 { 369 if (is_caller_secure(flags)) 370 return SMC_UNK; 371 372 /* Check the fid against the capabilities */ 373 if (!(psci_caps & define_psci_cap(smc_fid))) 374 return SMC_UNK; 375 376 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 377 /* 32-bit PSCI function, clear top parameter bits */ 378 379 x1 = (uint32_t)x1; 380 x2 = (uint32_t)x2; 381 x3 = (uint32_t)x3; 382 383 switch (smc_fid) { 384 case PSCI_VERSION: 385 return psci_version(); 386 387 case PSCI_CPU_OFF: 388 return psci_cpu_off(); 389 390 case PSCI_CPU_SUSPEND_AARCH32: 391 return psci_cpu_suspend(x1, x2, x3); 392 393 case PSCI_CPU_ON_AARCH32: 394 return psci_cpu_on(x1, x2, x3); 395 396 case PSCI_AFFINITY_INFO_AARCH32: 397 return psci_affinity_info(x1, x2); 398 399 case PSCI_MIG_AARCH32: 400 return psci_migrate(x1); 401 402 case PSCI_MIG_INFO_TYPE: 403 return psci_migrate_info_type(); 404 405 case PSCI_MIG_INFO_UP_CPU_AARCH32: 406 return psci_migrate_info_up_cpu(); 407 408 case PSCI_NODE_HW_STATE_AARCH32: 409 return psci_node_hw_state(x1, x2); 410 411 case PSCI_SYSTEM_SUSPEND_AARCH32: 412 return psci_system_suspend(x1, x2); 413 414 case PSCI_SYSTEM_OFF: 415 psci_system_off(); 416 /* We should never return from psci_system_off() */ 417 418 case PSCI_SYSTEM_RESET: 419 psci_system_reset(); 420 /* We should never return from psci_system_reset() */ 421 422 case PSCI_FEATURES: 423 return psci_features(x1); 424 425 #if ENABLE_PSCI_STAT 426 case PSCI_STAT_RESIDENCY_AARCH32: 427 return psci_stat_residency(x1, x2); 428 429 case PSCI_STAT_COUNT_AARCH32: 430 return psci_stat_count(x1, x2); 431 #endif 432 case PSCI_MEM_PROTECT: 433 return psci_mem_protect(x1); 434 435 case PSCI_MEM_CHK_RANGE_AARCH32: 436 return psci_mem_chk_range(x1, x2); 437 438 case PSCI_SYSTEM_RESET2_AARCH32: 439 /* We should never return from psci_system_reset2() */ 440 return psci_system_reset2(x1, x2); 441 442 default: 443 break; 444 } 445 } else { 446 /* 64-bit PSCI function */ 447 448 switch (smc_fid) { 449 case PSCI_CPU_SUSPEND_AARCH64: 450 return psci_cpu_suspend(x1, x2, x3); 451 452 case PSCI_CPU_ON_AARCH64: 453 return psci_cpu_on(x1, x2, x3); 454 455 case PSCI_AFFINITY_INFO_AARCH64: 456 return psci_affinity_info(x1, x2); 457 458 case PSCI_MIG_AARCH64: 459 return psci_migrate(x1); 460 461 case PSCI_MIG_INFO_UP_CPU_AARCH64: 462 return psci_migrate_info_up_cpu(); 463 464 case PSCI_NODE_HW_STATE_AARCH64: 465 return psci_node_hw_state(x1, x2); 466 467 case PSCI_SYSTEM_SUSPEND_AARCH64: 468 return psci_system_suspend(x1, x2); 469 470 #if ENABLE_PSCI_STAT 471 case PSCI_STAT_RESIDENCY_AARCH64: 472 return psci_stat_residency(x1, x2); 473 474 case PSCI_STAT_COUNT_AARCH64: 475 return psci_stat_count(x1, x2); 476 #endif 477 478 case PSCI_MEM_CHK_RANGE_AARCH64: 479 return psci_mem_chk_range(x1, x2); 480 481 case PSCI_SYSTEM_RESET2_AARCH64: 482 /* We should never return from psci_system_reset2() */ 483 return psci_system_reset2(x1, x2); 484 485 default: 486 break; 487 } 488 } 489 490 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); 491 return SMC_UNK; 492 } 493