1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <platform.h> 36 #include <runtime_svc.h> 37 #include <std_svc.h> 38 #include <string.h> 39 #include "psci_private.h" 40 41 /******************************************************************************* 42 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 43 ******************************************************************************/ 44 int psci_cpu_on(u_register_t target_cpu, 45 uintptr_t entrypoint, 46 u_register_t context_id) 47 48 { 49 int rc; 50 entry_point_info_t ep; 51 52 /* Determine if the cpu exists of not */ 53 rc = psci_validate_mpidr(target_cpu); 54 if (rc != PSCI_E_SUCCESS) 55 return PSCI_E_INVALID_PARAMS; 56 57 /* Validate the entry point and get the entry_point_info */ 58 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 59 if (rc != PSCI_E_SUCCESS) 60 return rc; 61 62 /* 63 * To turn this cpu on, specify which power 64 * levels need to be turned on 65 */ 66 return psci_cpu_on_start(target_cpu, &ep); 67 } 68 69 unsigned int psci_version(void) 70 { 71 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 72 } 73 74 int psci_cpu_suspend(unsigned int power_state, 75 uintptr_t entrypoint, 76 u_register_t context_id) 77 { 78 int rc; 79 unsigned int target_pwrlvl, is_power_down_state; 80 entry_point_info_t ep; 81 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 82 plat_local_state_t cpu_pd_state; 83 84 /* Validate the power_state parameter */ 85 rc = psci_validate_power_state(power_state, &state_info); 86 if (rc != PSCI_E_SUCCESS) { 87 assert(rc == PSCI_E_INVALID_PARAMS); 88 return rc; 89 } 90 91 /* 92 * Get the value of the state type bit from the power state parameter. 93 */ 94 is_power_down_state = psci_get_pstate_type(power_state); 95 96 /* Sanity check the requested suspend levels */ 97 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 98 == PSCI_E_SUCCESS); 99 100 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 101 102 /* Fast path for CPU standby.*/ 103 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 104 if (!psci_plat_pm_ops->cpu_standby) 105 return PSCI_E_INVALID_PARAMS; 106 107 /* 108 * Set the state of the CPU power domain to the platform 109 * specific retention state and enter the standby state. 110 */ 111 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 112 psci_set_cpu_local_state(cpu_pd_state); 113 114 #if ENABLE_PSCI_STAT 115 /* 116 * Capture time-stamp before CPU standby 117 * No cache maintenance is needed as caches 118 * are ON through out the CPU standby operation. 119 */ 120 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, 121 PMF_NO_CACHE_MAINT); 122 #endif 123 124 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 125 126 /* Upon exit from standby, set the state back to RUN. */ 127 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 128 129 #if ENABLE_PSCI_STAT 130 /* Capture time-stamp after CPU standby */ 131 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, 132 PMF_NO_CACHE_MAINT); 133 134 /* Update PSCI stats */ 135 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info, 136 PMF_NO_CACHE_MAINT); 137 #endif 138 139 return PSCI_E_SUCCESS; 140 } 141 142 /* 143 * If a power down state has been requested, we need to verify entry 144 * point and program entry information. 145 */ 146 if (is_power_down_state) { 147 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 148 if (rc != PSCI_E_SUCCESS) 149 return rc; 150 } 151 152 /* 153 * Do what is needed to enter the power down state. Upon success, 154 * enter the final wfi which will power down this CPU. This function 155 * might return if the power down was abandoned for any reason, e.g. 156 * arrival of an interrupt 157 */ 158 psci_cpu_suspend_start(&ep, 159 target_pwrlvl, 160 &state_info, 161 is_power_down_state); 162 163 return PSCI_E_SUCCESS; 164 } 165 166 167 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 168 { 169 int rc; 170 psci_power_state_t state_info; 171 entry_point_info_t ep; 172 173 /* Check if the current CPU is the last ON CPU in the system */ 174 if (!psci_is_last_on_cpu()) 175 return PSCI_E_DENIED; 176 177 /* Validate the entry point and get the entry_point_info */ 178 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 179 if (rc != PSCI_E_SUCCESS) 180 return rc; 181 182 /* Query the psci_power_state for system suspend */ 183 psci_query_sys_suspend_pwrstate(&state_info); 184 185 /* Ensure that the psci_power_state makes sense */ 186 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); 187 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 188 == PSCI_E_SUCCESS); 189 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); 190 191 /* 192 * Do what is needed to enter the system suspend state. This function 193 * might return if the power down was abandoned for any reason, e.g. 194 * arrival of an interrupt 195 */ 196 psci_cpu_suspend_start(&ep, 197 PLAT_MAX_PWR_LVL, 198 &state_info, 199 PSTATE_TYPE_POWERDOWN); 200 201 return PSCI_E_SUCCESS; 202 } 203 204 int psci_cpu_off(void) 205 { 206 int rc; 207 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 208 209 /* 210 * Do what is needed to power off this CPU and possible higher power 211 * levels if it able to do so. Upon success, enter the final wfi 212 * which will power down this CPU. 213 */ 214 rc = psci_do_cpu_off(target_pwrlvl); 215 216 /* 217 * The only error cpu_off can return is E_DENIED. So check if that's 218 * indeed the case. 219 */ 220 assert(rc == PSCI_E_DENIED); 221 222 return rc; 223 } 224 225 int psci_affinity_info(u_register_t target_affinity, 226 unsigned int lowest_affinity_level) 227 { 228 unsigned int target_idx; 229 230 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 231 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 232 return PSCI_E_INVALID_PARAMS; 233 234 /* Calculate the cpu index of the target */ 235 target_idx = plat_core_pos_by_mpidr(target_affinity); 236 if (target_idx == -1) 237 return PSCI_E_INVALID_PARAMS; 238 239 return psci_get_aff_info_state_by_idx(target_idx); 240 } 241 242 int psci_migrate(u_register_t target_cpu) 243 { 244 int rc; 245 u_register_t resident_cpu_mpidr; 246 247 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 248 if (rc != PSCI_TOS_UP_MIG_CAP) 249 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 250 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 251 252 /* 253 * Migrate should only be invoked on the CPU where 254 * the Secure OS is resident. 255 */ 256 if (resident_cpu_mpidr != read_mpidr_el1()) 257 return PSCI_E_NOT_PRESENT; 258 259 /* Check the validity of the specified target cpu */ 260 rc = psci_validate_mpidr(target_cpu); 261 if (rc != PSCI_E_SUCCESS) 262 return PSCI_E_INVALID_PARAMS; 263 264 assert(psci_spd_pm && psci_spd_pm->svc_migrate); 265 266 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 267 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 268 269 return rc; 270 } 271 272 int psci_migrate_info_type(void) 273 { 274 u_register_t resident_cpu_mpidr; 275 276 return psci_spd_migrate_info(&resident_cpu_mpidr); 277 } 278 279 long psci_migrate_info_up_cpu(void) 280 { 281 u_register_t resident_cpu_mpidr; 282 int rc; 283 284 /* 285 * Return value of this depends upon what 286 * psci_spd_migrate_info() returns. 287 */ 288 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 289 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) 290 return PSCI_E_INVALID_PARAMS; 291 292 return resident_cpu_mpidr; 293 } 294 295 int psci_features(unsigned int psci_fid) 296 { 297 unsigned int local_caps = psci_caps; 298 299 /* Check if it is a 64 bit function */ 300 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 301 local_caps &= PSCI_CAP_64BIT_MASK; 302 303 /* Check for invalid fid */ 304 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 305 && is_psci_fid(psci_fid))) 306 return PSCI_E_NOT_SUPPORTED; 307 308 309 /* Check if the psci fid is supported or not */ 310 if (!(local_caps & define_psci_cap(psci_fid))) 311 return PSCI_E_NOT_SUPPORTED; 312 313 /* Format the feature flags */ 314 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || 315 psci_fid == PSCI_CPU_SUSPEND_AARCH64) { 316 /* 317 * The trusted firmware does not support OS Initiated Mode. 318 */ 319 return (FF_PSTATE << FF_PSTATE_SHIFT) | 320 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); 321 } 322 323 /* Return 0 for all other fid's */ 324 return PSCI_E_SUCCESS; 325 } 326 327 /******************************************************************************* 328 * PSCI top level handler for servicing SMCs. 329 ******************************************************************************/ 330 uintptr_t psci_smc_handler(uint32_t smc_fid, 331 u_register_t x1, 332 u_register_t x2, 333 u_register_t x3, 334 u_register_t x4, 335 void *cookie, 336 void *handle, 337 u_register_t flags) 338 { 339 if (is_caller_secure(flags)) 340 SMC_RET1(handle, SMC_UNK); 341 342 /* Check the fid against the capabilities */ 343 if (!(psci_caps & define_psci_cap(smc_fid))) 344 SMC_RET1(handle, SMC_UNK); 345 346 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 347 /* 32-bit PSCI function, clear top parameter bits */ 348 349 x1 = (uint32_t)x1; 350 x2 = (uint32_t)x2; 351 x3 = (uint32_t)x3; 352 353 switch (smc_fid) { 354 case PSCI_VERSION: 355 SMC_RET1(handle, psci_version()); 356 357 case PSCI_CPU_OFF: 358 SMC_RET1(handle, psci_cpu_off()); 359 360 case PSCI_CPU_SUSPEND_AARCH32: 361 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); 362 363 case PSCI_CPU_ON_AARCH32: 364 SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); 365 366 case PSCI_AFFINITY_INFO_AARCH32: 367 SMC_RET1(handle, psci_affinity_info(x1, x2)); 368 369 case PSCI_MIG_AARCH32: 370 SMC_RET1(handle, psci_migrate(x1)); 371 372 case PSCI_MIG_INFO_TYPE: 373 SMC_RET1(handle, psci_migrate_info_type()); 374 375 case PSCI_MIG_INFO_UP_CPU_AARCH32: 376 SMC_RET1(handle, psci_migrate_info_up_cpu()); 377 378 case PSCI_SYSTEM_SUSPEND_AARCH32: 379 SMC_RET1(handle, psci_system_suspend(x1, x2)); 380 381 case PSCI_SYSTEM_OFF: 382 psci_system_off(); 383 /* We should never return from psci_system_off() */ 384 385 case PSCI_SYSTEM_RESET: 386 psci_system_reset(); 387 /* We should never return from psci_system_reset() */ 388 389 case PSCI_FEATURES: 390 SMC_RET1(handle, psci_features(x1)); 391 392 #if ENABLE_PSCI_STAT 393 case PSCI_STAT_RESIDENCY_AARCH32: 394 SMC_RET1(handle, psci_stat_residency(x1, x2)); 395 396 case PSCI_STAT_COUNT_AARCH32: 397 SMC_RET1(handle, psci_stat_count(x1, x2)); 398 #endif 399 400 default: 401 break; 402 } 403 } else { 404 /* 64-bit PSCI function */ 405 406 switch (smc_fid) { 407 case PSCI_CPU_SUSPEND_AARCH64: 408 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); 409 410 case PSCI_CPU_ON_AARCH64: 411 SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); 412 413 case PSCI_AFFINITY_INFO_AARCH64: 414 SMC_RET1(handle, psci_affinity_info(x1, x2)); 415 416 case PSCI_MIG_AARCH64: 417 SMC_RET1(handle, psci_migrate(x1)); 418 419 case PSCI_MIG_INFO_UP_CPU_AARCH64: 420 SMC_RET1(handle, psci_migrate_info_up_cpu()); 421 422 case PSCI_SYSTEM_SUSPEND_AARCH64: 423 SMC_RET1(handle, psci_system_suspend(x1, x2)); 424 425 #if ENABLE_PSCI_STAT 426 case PSCI_STAT_RESIDENCY_AARCH64: 427 SMC_RET1(handle, psci_stat_residency(x1, x2)); 428 429 case PSCI_STAT_COUNT_AARCH64: 430 SMC_RET1(handle, psci_stat_count(x1, x2)); 431 #endif 432 433 default: 434 break; 435 } 436 } 437 438 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); 439 SMC_RET1(handle, SMC_UNK); 440 } 441