1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/pmf/pmf.h> 14 #include <lib/runtime_instr.h> 15 #include <lib/smccc.h> 16 #include <plat/common/platform.h> 17 #include <services/arm_arch_svc.h> 18 19 #include "psci_private.h" 20 21 /******************************************************************************* 22 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 23 ******************************************************************************/ 24 int psci_cpu_on(u_register_t target_cpu, 25 uintptr_t entrypoint, 26 u_register_t context_id) 27 28 { 29 int rc; 30 entry_point_info_t ep; 31 32 /* Validate the target CPU */ 33 if (!is_valid_mpidr(target_cpu)) 34 return PSCI_E_INVALID_PARAMS; 35 36 /* Validate the entry point and get the entry_point_info */ 37 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 38 if (rc != PSCI_E_SUCCESS) 39 return rc; 40 41 /* 42 * To turn this cpu on, specify which power 43 * levels need to be turned on 44 */ 45 return psci_cpu_on_start(target_cpu, &ep); 46 } 47 48 unsigned int psci_version(void) 49 { 50 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 51 } 52 53 int psci_cpu_suspend(unsigned int power_state, 54 uintptr_t entrypoint, 55 u_register_t context_id) 56 { 57 int rc; 58 unsigned int target_pwrlvl, is_power_down_state; 59 entry_point_info_t ep; 60 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 61 plat_local_state_t cpu_pd_state; 62 unsigned int cpu_idx = plat_my_core_pos(); 63 #if PSCI_OS_INIT_MODE 64 plat_local_state_t prev[PLAT_MAX_PWR_LVL]; 65 #endif 66 67 /* Validate the power_state parameter */ 68 rc = psci_validate_power_state(power_state, &state_info); 69 if (rc != PSCI_E_SUCCESS) { 70 assert(rc == PSCI_E_INVALID_PARAMS); 71 return rc; 72 } 73 74 /* 75 * Get the value of the state type bit from the power state parameter. 76 */ 77 is_power_down_state = psci_get_pstate_type(power_state); 78 79 /* Sanity check the requested suspend levels */ 80 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 81 == PSCI_E_SUCCESS); 82 83 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 84 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 85 ERROR("Invalid target power level for suspend operation\n"); 86 panic(); 87 } 88 89 /* Fast path for CPU standby.*/ 90 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 91 if (psci_plat_pm_ops->cpu_standby == NULL) 92 return PSCI_E_INVALID_PARAMS; 93 94 /* 95 * Set the state of the CPU power domain to the platform 96 * specific retention state and enter the standby state. 97 */ 98 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 99 psci_set_cpu_local_state(cpu_pd_state); 100 101 #if PSCI_OS_INIT_MODE 102 /* 103 * If in OS-initiated mode, save a copy of the previous 104 * requested local power states and update the new requested 105 * local power states for this CPU. 106 */ 107 if (psci_suspend_mode == OS_INIT) { 108 psci_update_req_local_pwr_states(target_pwrlvl, cpu_idx, 109 &state_info, prev); 110 } 111 #endif 112 113 #if ENABLE_PSCI_STAT 114 plat_psci_stat_accounting_start(&state_info); 115 #endif 116 117 #if ENABLE_RUNTIME_INSTRUMENTATION 118 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 119 RT_INSTR_ENTER_HW_LOW_PWR, 120 PMF_NO_CACHE_MAINT); 121 #endif 122 123 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 124 125 /* Upon exit from standby, set the state back to RUN. */ 126 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 127 128 #if PSCI_OS_INIT_MODE 129 /* 130 * If in OS-initiated mode, restore the previous requested 131 * local power states for this CPU. 132 */ 133 if (psci_suspend_mode == OS_INIT) { 134 psci_restore_req_local_pwr_states(cpu_idx, prev); 135 } 136 #endif 137 138 #if ENABLE_RUNTIME_INSTRUMENTATION 139 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 140 RT_INSTR_EXIT_HW_LOW_PWR, 141 PMF_NO_CACHE_MAINT); 142 #endif 143 144 #if ENABLE_PSCI_STAT 145 plat_psci_stat_accounting_stop(&state_info); 146 147 /* Update PSCI stats */ 148 psci_stats_update_pwr_up(cpu_idx, PSCI_CPU_PWR_LVL, &state_info); 149 #endif 150 151 return PSCI_E_SUCCESS; 152 } 153 154 /* 155 * If a power down state has been requested, we need to verify entry 156 * point and program entry information. 157 */ 158 if (is_power_down_state != 0U) { 159 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 160 if (rc != PSCI_E_SUCCESS) 161 return rc; 162 } 163 164 /* 165 * Do what is needed to enter the power down state. Upon success, 166 * enter the final wfi which will power down this CPU. This function 167 * might return if the power down was abandoned for any reason, e.g. 168 * arrival of an interrupt 169 */ 170 rc = psci_cpu_suspend_start(cpu_idx, 171 &ep, 172 target_pwrlvl, 173 &state_info, 174 is_power_down_state); 175 176 return rc; 177 } 178 179 180 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 181 { 182 int rc; 183 psci_power_state_t state_info; 184 entry_point_info_t ep; 185 unsigned int cpu_idx = plat_my_core_pos(); 186 187 /* Check if the current CPU is the last ON CPU in the system */ 188 if (!psci_is_last_on_cpu(cpu_idx)) 189 return PSCI_E_DENIED; 190 191 /* Validate the entry point and get the entry_point_info */ 192 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 193 if (rc != PSCI_E_SUCCESS) 194 return rc; 195 196 /* Query the psci_power_state for system suspend */ 197 psci_query_sys_suspend_pwrstate(&state_info); 198 199 /* 200 * Check if platform allows suspend to Highest power level 201 * (System level) 202 */ 203 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) 204 return PSCI_E_DENIED; 205 206 /* Ensure that the psci_power_state makes sense */ 207 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 208 == PSCI_E_SUCCESS); 209 assert(is_local_state_off( 210 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); 211 212 /* 213 * Do what is needed to enter the system suspend state. This function 214 * might return if the power down was abandoned for any reason, e.g. 215 * arrival of an interrupt 216 */ 217 rc = psci_cpu_suspend_start(cpu_idx, 218 &ep, 219 PLAT_MAX_PWR_LVL, 220 &state_info, 221 PSTATE_TYPE_POWERDOWN); 222 223 return rc; 224 } 225 226 int psci_cpu_off(void) 227 { 228 int rc; 229 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 230 231 /* 232 * Do what is needed to power off this CPU and possible higher power 233 * levels if it able to do so. Upon success, enter the final wfi 234 * which will power down this CPU. 235 */ 236 rc = psci_do_cpu_off(target_pwrlvl); 237 238 /* 239 * The only error cpu_off can return is E_DENIED. So check if that's 240 * indeed the case. 241 */ 242 assert(rc == PSCI_E_DENIED); 243 244 return rc; 245 } 246 247 int psci_affinity_info(u_register_t target_affinity, 248 unsigned int lowest_affinity_level) 249 { 250 unsigned int target_idx; 251 252 /* Validate the target affinity */ 253 if (!is_valid_mpidr(target_affinity)) 254 return PSCI_E_INVALID_PARAMS; 255 256 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 257 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 258 return PSCI_E_INVALID_PARAMS; 259 260 /* Calculate the cpu index of the target */ 261 target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity); 262 263 /* 264 * Generic management: 265 * Perform cache maintanence ahead of reading the target CPU state to 266 * ensure that the data is not stale. 267 * There is a theoretical edge case where the cache may contain stale 268 * data for the target CPU data - this can occur under the following 269 * conditions: 270 * - the target CPU is in another cluster from the current 271 * - the target CPU was the last CPU to shutdown on its cluster 272 * - the cluster was removed from coherency as part of the CPU shutdown 273 * 274 * In this case the cache maintenace that was performed as part of the 275 * target CPUs shutdown was not seen by the current CPU's cluster. And 276 * so the cache may contain stale data for the target CPU. 277 */ 278 flush_cpu_data_by_index(target_idx, 279 psci_svc_cpu_data.aff_info_state); 280 281 return psci_get_aff_info_state_by_idx(target_idx); 282 } 283 284 int psci_migrate(u_register_t target_cpu) 285 { 286 int rc; 287 u_register_t resident_cpu_mpidr; 288 289 /* Validate the target cpu */ 290 if (!is_valid_mpidr(target_cpu)) 291 return PSCI_E_INVALID_PARAMS; 292 293 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 294 if (rc != PSCI_TOS_UP_MIG_CAP) 295 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 296 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 297 298 /* 299 * Migrate should only be invoked on the CPU where 300 * the Secure OS is resident. 301 */ 302 if (resident_cpu_mpidr != read_mpidr_el1()) 303 return PSCI_E_NOT_PRESENT; 304 305 /* Check the validity of the specified target cpu */ 306 if (!is_valid_mpidr(target_cpu)) 307 return PSCI_E_INVALID_PARAMS; 308 309 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); 310 311 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 312 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 313 314 return rc; 315 } 316 317 int psci_migrate_info_type(void) 318 { 319 u_register_t resident_cpu_mpidr; 320 321 return psci_spd_migrate_info(&resident_cpu_mpidr); 322 } 323 324 u_register_t psci_migrate_info_up_cpu(void) 325 { 326 u_register_t resident_cpu_mpidr; 327 int rc; 328 329 /* 330 * Return value of this depends upon what 331 * psci_spd_migrate_info() returns. 332 */ 333 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 334 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP)) 335 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS; 336 337 return resident_cpu_mpidr; 338 } 339 340 int psci_node_hw_state(u_register_t target_cpu, 341 unsigned int power_level) 342 { 343 int rc; 344 345 /* Validate target_cpu */ 346 if (!is_valid_mpidr(target_cpu)) 347 return PSCI_E_INVALID_PARAMS; 348 349 /* Validate power_level against PLAT_MAX_PWR_LVL */ 350 if (power_level > PLAT_MAX_PWR_LVL) 351 return PSCI_E_INVALID_PARAMS; 352 353 /* 354 * Dispatch this call to platform to query power controller, and pass on 355 * to the caller what it returns 356 */ 357 assert(psci_plat_pm_ops->get_node_hw_state != NULL); 358 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 359 assert(((rc >= HW_ON) && (rc <= HW_STANDBY)) 360 || (rc == PSCI_E_NOT_SUPPORTED) 361 || (rc == PSCI_E_INVALID_PARAMS)); 362 return rc; 363 } 364 365 int psci_features(unsigned int psci_fid) 366 { 367 unsigned int local_caps = psci_caps; 368 369 if (psci_fid == SMCCC_VERSION) 370 return PSCI_E_SUCCESS; 371 372 /* Check if it is a 64 bit function */ 373 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 374 local_caps &= PSCI_CAP_64BIT_MASK; 375 376 /* Check for invalid fid */ 377 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 378 && is_psci_fid(psci_fid))) 379 return PSCI_E_NOT_SUPPORTED; 380 381 382 /* Check if the psci fid is supported or not */ 383 if ((local_caps & define_psci_cap(psci_fid)) == 0U) 384 return PSCI_E_NOT_SUPPORTED; 385 386 /* Format the feature flags */ 387 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) || 388 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) { 389 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) | 390 (FF_SUPPORTS_OS_INIT_MODE << FF_MODE_SUPPORT_SHIFT)); 391 return (int)ret; 392 } 393 394 /* Return 0 for all other fid's */ 395 return PSCI_E_SUCCESS; 396 } 397 398 #if PSCI_OS_INIT_MODE 399 int psci_set_suspend_mode(unsigned int mode) 400 { 401 if (psci_suspend_mode == mode) { 402 return PSCI_E_SUCCESS; 403 } 404 405 unsigned int this_core = plat_my_core_pos(); 406 407 if (mode == PLAT_COORD) { 408 /* Check if the current CPU is the last ON CPU in the system */ 409 if (!psci_is_last_on_cpu_safe(this_core)) { 410 return PSCI_E_DENIED; 411 } 412 } 413 414 if (mode == OS_INIT) { 415 /* 416 * Check if all CPUs in the system are ON or if the current 417 * CPU is the last ON CPU in the system. 418 */ 419 if (!(psci_are_all_cpus_on_safe(this_core) || 420 psci_is_last_on_cpu_safe(this_core))) { 421 return PSCI_E_DENIED; 422 } 423 } 424 425 psci_suspend_mode = mode; 426 psci_flush_dcache_range((uintptr_t)&psci_suspend_mode, 427 sizeof(psci_suspend_mode)); 428 429 return PSCI_E_SUCCESS; 430 } 431 #endif 432 433 /******************************************************************************* 434 * PSCI top level handler for servicing SMCs. 435 ******************************************************************************/ 436 u_register_t psci_smc_handler(uint32_t smc_fid, 437 u_register_t x1, 438 u_register_t x2, 439 u_register_t x3, 440 u_register_t x4, 441 void *cookie, 442 void *handle, 443 u_register_t flags) 444 { 445 u_register_t ret; 446 447 if (is_caller_secure(flags)) 448 return (u_register_t)SMC_UNK; 449 450 /* Check the fid against the capabilities */ 451 if ((psci_caps & define_psci_cap(smc_fid)) == 0U) 452 return (u_register_t)SMC_UNK; 453 454 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 455 /* 32-bit PSCI function, clear top parameter bits */ 456 457 uint32_t r1 = (uint32_t)x1; 458 uint32_t r2 = (uint32_t)x2; 459 uint32_t r3 = (uint32_t)x3; 460 461 switch (smc_fid) { 462 case PSCI_VERSION: 463 ret = (u_register_t)psci_version(); 464 break; 465 466 case PSCI_CPU_OFF: 467 ret = (u_register_t)psci_cpu_off(); 468 break; 469 470 case PSCI_CPU_SUSPEND_AARCH32: 471 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3); 472 break; 473 474 case PSCI_CPU_ON_AARCH32: 475 ret = (u_register_t)psci_cpu_on(r1, r2, r3); 476 break; 477 478 case PSCI_AFFINITY_INFO_AARCH32: 479 ret = (u_register_t)psci_affinity_info(r1, r2); 480 break; 481 482 case PSCI_MIG_AARCH32: 483 ret = (u_register_t)psci_migrate(r1); 484 break; 485 486 case PSCI_MIG_INFO_TYPE: 487 ret = (u_register_t)psci_migrate_info_type(); 488 break; 489 490 case PSCI_MIG_INFO_UP_CPU_AARCH32: 491 ret = psci_migrate_info_up_cpu(); 492 break; 493 494 case PSCI_NODE_HW_STATE_AARCH32: 495 ret = (u_register_t)psci_node_hw_state(r1, r2); 496 break; 497 498 case PSCI_SYSTEM_SUSPEND_AARCH32: 499 ret = (u_register_t)psci_system_suspend(r1, r2); 500 break; 501 502 case PSCI_SYSTEM_OFF: 503 psci_system_off(); 504 /* We should never return from psci_system_off() */ 505 break; 506 507 case PSCI_SYSTEM_RESET: 508 psci_system_reset(); 509 /* We should never return from psci_system_reset() */ 510 break; 511 512 case PSCI_FEATURES: 513 ret = (u_register_t)psci_features(r1); 514 break; 515 516 #if PSCI_OS_INIT_MODE 517 case PSCI_SET_SUSPEND_MODE: 518 ret = (u_register_t)psci_set_suspend_mode(r1); 519 break; 520 #endif 521 522 #if ENABLE_PSCI_STAT 523 case PSCI_STAT_RESIDENCY_AARCH32: 524 ret = psci_stat_residency(r1, r2); 525 break; 526 527 case PSCI_STAT_COUNT_AARCH32: 528 ret = psci_stat_count(r1, r2); 529 break; 530 #endif 531 case PSCI_MEM_PROTECT: 532 ret = psci_mem_protect(r1); 533 break; 534 535 case PSCI_MEM_CHK_RANGE_AARCH32: 536 ret = psci_mem_chk_range(r1, r2); 537 break; 538 539 case PSCI_SYSTEM_RESET2_AARCH32: 540 /* We should never return from psci_system_reset2() */ 541 ret = psci_system_reset2(r1, r2); 542 break; 543 544 default: 545 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 546 ret = (u_register_t)SMC_UNK; 547 break; 548 } 549 } else { 550 /* 64-bit PSCI function */ 551 552 switch (smc_fid) { 553 case PSCI_CPU_SUSPEND_AARCH64: 554 ret = (u_register_t) 555 psci_cpu_suspend((unsigned int)x1, x2, x3); 556 break; 557 558 case PSCI_CPU_ON_AARCH64: 559 ret = (u_register_t)psci_cpu_on(x1, x2, x3); 560 break; 561 562 case PSCI_AFFINITY_INFO_AARCH64: 563 ret = (u_register_t) 564 psci_affinity_info(x1, (unsigned int)x2); 565 break; 566 567 case PSCI_MIG_AARCH64: 568 ret = (u_register_t)psci_migrate(x1); 569 break; 570 571 case PSCI_MIG_INFO_UP_CPU_AARCH64: 572 ret = psci_migrate_info_up_cpu(); 573 break; 574 575 case PSCI_NODE_HW_STATE_AARCH64: 576 ret = (u_register_t)psci_node_hw_state( 577 x1, (unsigned int) x2); 578 break; 579 580 case PSCI_SYSTEM_SUSPEND_AARCH64: 581 ret = (u_register_t)psci_system_suspend(x1, x2); 582 break; 583 584 #if ENABLE_PSCI_STAT 585 case PSCI_STAT_RESIDENCY_AARCH64: 586 ret = psci_stat_residency(x1, (unsigned int) x2); 587 break; 588 589 case PSCI_STAT_COUNT_AARCH64: 590 ret = psci_stat_count(x1, (unsigned int) x2); 591 break; 592 #endif 593 594 case PSCI_MEM_CHK_RANGE_AARCH64: 595 ret = psci_mem_chk_range(x1, x2); 596 break; 597 598 case PSCI_SYSTEM_RESET2_AARCH64: 599 /* We should never return from psci_system_reset2() */ 600 ret = psci_system_reset2((uint32_t) x1, x2); 601 break; 602 603 default: 604 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 605 ret = (u_register_t)SMC_UNK; 606 break; 607 } 608 } 609 610 return ret; 611 } 612