1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <platform.h> 36 #include <smcc.h> 37 #include <string.h> 38 #include "psci_private.h" 39 40 /******************************************************************************* 41 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 42 ******************************************************************************/ 43 int psci_cpu_on(u_register_t target_cpu, 44 uintptr_t entrypoint, 45 u_register_t context_id) 46 47 { 48 int rc; 49 entry_point_info_t ep; 50 51 /* Determine if the cpu exists of not */ 52 rc = psci_validate_mpidr(target_cpu); 53 if (rc != PSCI_E_SUCCESS) 54 return PSCI_E_INVALID_PARAMS; 55 56 /* Validate the entry point and get the entry_point_info */ 57 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 58 if (rc != PSCI_E_SUCCESS) 59 return rc; 60 61 /* 62 * To turn this cpu on, specify which power 63 * levels need to be turned on 64 */ 65 return psci_cpu_on_start(target_cpu, &ep); 66 } 67 68 unsigned int psci_version(void) 69 { 70 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 71 } 72 73 int psci_cpu_suspend(unsigned int power_state, 74 uintptr_t entrypoint, 75 u_register_t context_id) 76 { 77 int rc; 78 unsigned int target_pwrlvl, is_power_down_state; 79 entry_point_info_t ep; 80 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 81 plat_local_state_t cpu_pd_state; 82 83 /* Validate the power_state parameter */ 84 rc = psci_validate_power_state(power_state, &state_info); 85 if (rc != PSCI_E_SUCCESS) { 86 assert(rc == PSCI_E_INVALID_PARAMS); 87 return rc; 88 } 89 90 /* 91 * Get the value of the state type bit from the power state parameter. 92 */ 93 is_power_down_state = psci_get_pstate_type(power_state); 94 95 /* Sanity check the requested suspend levels */ 96 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 97 == PSCI_E_SUCCESS); 98 99 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 100 101 /* Fast path for CPU standby.*/ 102 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 103 if (!psci_plat_pm_ops->cpu_standby) 104 return PSCI_E_INVALID_PARAMS; 105 106 /* 107 * Set the state of the CPU power domain to the platform 108 * specific retention state and enter the standby state. 109 */ 110 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 111 psci_set_cpu_local_state(cpu_pd_state); 112 113 #if ENABLE_PSCI_STAT 114 /* 115 * Capture time-stamp before CPU standby 116 * No cache maintenance is needed as caches 117 * are ON through out the CPU standby operation. 118 */ 119 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, 120 PMF_NO_CACHE_MAINT); 121 #endif 122 123 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 124 125 /* Upon exit from standby, set the state back to RUN. */ 126 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 127 128 #if ENABLE_PSCI_STAT 129 /* Capture time-stamp after CPU standby */ 130 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, 131 PMF_NO_CACHE_MAINT); 132 133 /* Update PSCI stats */ 134 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info, 135 PMF_NO_CACHE_MAINT); 136 #endif 137 138 return PSCI_E_SUCCESS; 139 } 140 141 /* 142 * If a power down state has been requested, we need to verify entry 143 * point and program entry information. 144 */ 145 if (is_power_down_state) { 146 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 147 if (rc != PSCI_E_SUCCESS) 148 return rc; 149 } 150 151 /* 152 * Do what is needed to enter the power down state. Upon success, 153 * enter the final wfi which will power down this CPU. This function 154 * might return if the power down was abandoned for any reason, e.g. 155 * arrival of an interrupt 156 */ 157 psci_cpu_suspend_start(&ep, 158 target_pwrlvl, 159 &state_info, 160 is_power_down_state); 161 162 return PSCI_E_SUCCESS; 163 } 164 165 166 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 167 { 168 int rc; 169 psci_power_state_t state_info; 170 entry_point_info_t ep; 171 172 /* Check if the current CPU is the last ON CPU in the system */ 173 if (!psci_is_last_on_cpu()) 174 return PSCI_E_DENIED; 175 176 /* Validate the entry point and get the entry_point_info */ 177 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 178 if (rc != PSCI_E_SUCCESS) 179 return rc; 180 181 /* Query the psci_power_state for system suspend */ 182 psci_query_sys_suspend_pwrstate(&state_info); 183 184 /* Ensure that the psci_power_state makes sense */ 185 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); 186 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 187 == PSCI_E_SUCCESS); 188 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); 189 190 /* 191 * Do what is needed to enter the system suspend state. This function 192 * might return if the power down was abandoned for any reason, e.g. 193 * arrival of an interrupt 194 */ 195 psci_cpu_suspend_start(&ep, 196 PLAT_MAX_PWR_LVL, 197 &state_info, 198 PSTATE_TYPE_POWERDOWN); 199 200 return PSCI_E_SUCCESS; 201 } 202 203 int psci_cpu_off(void) 204 { 205 int rc; 206 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 207 208 /* 209 * Do what is needed to power off this CPU and possible higher power 210 * levels if it able to do so. Upon success, enter the final wfi 211 * which will power down this CPU. 212 */ 213 rc = psci_do_cpu_off(target_pwrlvl); 214 215 /* 216 * The only error cpu_off can return is E_DENIED. So check if that's 217 * indeed the case. 218 */ 219 assert(rc == PSCI_E_DENIED); 220 221 return rc; 222 } 223 224 int psci_affinity_info(u_register_t target_affinity, 225 unsigned int lowest_affinity_level) 226 { 227 unsigned int target_idx; 228 229 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 230 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 231 return PSCI_E_INVALID_PARAMS; 232 233 /* Calculate the cpu index of the target */ 234 target_idx = plat_core_pos_by_mpidr(target_affinity); 235 if (target_idx == -1) 236 return PSCI_E_INVALID_PARAMS; 237 238 return psci_get_aff_info_state_by_idx(target_idx); 239 } 240 241 int psci_migrate(u_register_t target_cpu) 242 { 243 int rc; 244 u_register_t resident_cpu_mpidr; 245 246 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 247 if (rc != PSCI_TOS_UP_MIG_CAP) 248 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 249 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 250 251 /* 252 * Migrate should only be invoked on the CPU where 253 * the Secure OS is resident. 254 */ 255 if (resident_cpu_mpidr != read_mpidr_el1()) 256 return PSCI_E_NOT_PRESENT; 257 258 /* Check the validity of the specified target cpu */ 259 rc = psci_validate_mpidr(target_cpu); 260 if (rc != PSCI_E_SUCCESS) 261 return PSCI_E_INVALID_PARAMS; 262 263 assert(psci_spd_pm && psci_spd_pm->svc_migrate); 264 265 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 266 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 267 268 return rc; 269 } 270 271 int psci_migrate_info_type(void) 272 { 273 u_register_t resident_cpu_mpidr; 274 275 return psci_spd_migrate_info(&resident_cpu_mpidr); 276 } 277 278 long psci_migrate_info_up_cpu(void) 279 { 280 u_register_t resident_cpu_mpidr; 281 int rc; 282 283 /* 284 * Return value of this depends upon what 285 * psci_spd_migrate_info() returns. 286 */ 287 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 288 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) 289 return PSCI_E_INVALID_PARAMS; 290 291 return resident_cpu_mpidr; 292 } 293 294 int psci_features(unsigned int psci_fid) 295 { 296 unsigned int local_caps = psci_caps; 297 298 /* Check if it is a 64 bit function */ 299 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 300 local_caps &= PSCI_CAP_64BIT_MASK; 301 302 /* Check for invalid fid */ 303 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 304 && is_psci_fid(psci_fid))) 305 return PSCI_E_NOT_SUPPORTED; 306 307 308 /* Check if the psci fid is supported or not */ 309 if (!(local_caps & define_psci_cap(psci_fid))) 310 return PSCI_E_NOT_SUPPORTED; 311 312 /* Format the feature flags */ 313 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || 314 psci_fid == PSCI_CPU_SUSPEND_AARCH64) { 315 /* 316 * The trusted firmware does not support OS Initiated Mode. 317 */ 318 return (FF_PSTATE << FF_PSTATE_SHIFT) | 319 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); 320 } 321 322 /* Return 0 for all other fid's */ 323 return PSCI_E_SUCCESS; 324 } 325 326 /******************************************************************************* 327 * PSCI top level handler for servicing SMCs. 328 ******************************************************************************/ 329 u_register_t psci_smc_handler(uint32_t smc_fid, 330 u_register_t x1, 331 u_register_t x2, 332 u_register_t x3, 333 u_register_t x4, 334 void *cookie, 335 void *handle, 336 u_register_t flags) 337 { 338 if (is_caller_secure(flags)) 339 return SMC_UNK; 340 341 /* Check the fid against the capabilities */ 342 if (!(psci_caps & define_psci_cap(smc_fid))) 343 return SMC_UNK; 344 345 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 346 /* 32-bit PSCI function, clear top parameter bits */ 347 348 x1 = (uint32_t)x1; 349 x2 = (uint32_t)x2; 350 x3 = (uint32_t)x3; 351 352 switch (smc_fid) { 353 case PSCI_VERSION: 354 return psci_version(); 355 356 case PSCI_CPU_OFF: 357 return psci_cpu_off(); 358 359 case PSCI_CPU_SUSPEND_AARCH32: 360 return psci_cpu_suspend(x1, x2, x3); 361 362 case PSCI_CPU_ON_AARCH32: 363 return psci_cpu_on(x1, x2, x3); 364 365 case PSCI_AFFINITY_INFO_AARCH32: 366 return psci_affinity_info(x1, x2); 367 368 case PSCI_MIG_AARCH32: 369 return psci_migrate(x1); 370 371 case PSCI_MIG_INFO_TYPE: 372 return psci_migrate_info_type(); 373 374 case PSCI_MIG_INFO_UP_CPU_AARCH32: 375 return psci_migrate_info_up_cpu(); 376 377 case PSCI_SYSTEM_SUSPEND_AARCH32: 378 return psci_system_suspend(x1, x2); 379 380 case PSCI_SYSTEM_OFF: 381 psci_system_off(); 382 /* We should never return from psci_system_off() */ 383 384 case PSCI_SYSTEM_RESET: 385 psci_system_reset(); 386 /* We should never return from psci_system_reset() */ 387 388 case PSCI_FEATURES: 389 return psci_features(x1); 390 391 #if ENABLE_PSCI_STAT 392 case PSCI_STAT_RESIDENCY_AARCH32: 393 return psci_stat_residency(x1, x2); 394 395 case PSCI_STAT_COUNT_AARCH32: 396 return psci_stat_count(x1, x2); 397 #endif 398 399 default: 400 break; 401 } 402 } else { 403 /* 64-bit PSCI function */ 404 405 switch (smc_fid) { 406 case PSCI_CPU_SUSPEND_AARCH64: 407 return psci_cpu_suspend(x1, x2, x3); 408 409 case PSCI_CPU_ON_AARCH64: 410 return psci_cpu_on(x1, x2, x3); 411 412 case PSCI_AFFINITY_INFO_AARCH64: 413 return psci_affinity_info(x1, x2); 414 415 case PSCI_MIG_AARCH64: 416 return psci_migrate(x1); 417 418 case PSCI_MIG_INFO_UP_CPU_AARCH64: 419 return psci_migrate_info_up_cpu(); 420 421 case PSCI_SYSTEM_SUSPEND_AARCH64: 422 return psci_system_suspend(x1, x2); 423 424 #if ENABLE_PSCI_STAT 425 case PSCI_STAT_RESIDENCY_AARCH64: 426 return psci_stat_residency(x1, x2); 427 428 case PSCI_STAT_COUNT_AARCH64: 429 return psci_stat_count(x1, x2); 430 #endif 431 432 default: 433 break; 434 } 435 } 436 437 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); 438 return SMC_UNK; 439 } 440