1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_arch_svc.h> 10 #include <assert.h> 11 #include <debug.h> 12 #include <platform.h> 13 #include <pmf.h> 14 #include <runtime_instr.h> 15 #include <smccc.h> 16 #include <string.h> 17 #include "psci_private.h" 18 19 /******************************************************************************* 20 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 21 ******************************************************************************/ 22 int psci_cpu_on(u_register_t target_cpu, 23 uintptr_t entrypoint, 24 u_register_t context_id) 25 26 { 27 int rc; 28 entry_point_info_t ep; 29 30 /* Determine if the cpu exists of not */ 31 rc = psci_validate_mpidr(target_cpu); 32 if (rc != PSCI_E_SUCCESS) 33 return PSCI_E_INVALID_PARAMS; 34 35 /* Validate the entry point and get the entry_point_info */ 36 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 37 if (rc != PSCI_E_SUCCESS) 38 return rc; 39 40 /* 41 * To turn this cpu on, specify which power 42 * levels need to be turned on 43 */ 44 return psci_cpu_on_start(target_cpu, &ep); 45 } 46 47 unsigned int psci_version(void) 48 { 49 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 50 } 51 52 int psci_cpu_suspend(unsigned int power_state, 53 uintptr_t entrypoint, 54 u_register_t context_id) 55 { 56 int rc; 57 unsigned int target_pwrlvl, is_power_down_state; 58 entry_point_info_t ep; 59 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 60 plat_local_state_t cpu_pd_state; 61 62 /* Validate the power_state parameter */ 63 rc = psci_validate_power_state(power_state, &state_info); 64 if (rc != PSCI_E_SUCCESS) { 65 assert(rc == PSCI_E_INVALID_PARAMS); 66 return rc; 67 } 68 69 /* 70 * Get the value of the state type bit from the power state parameter. 71 */ 72 is_power_down_state = psci_get_pstate_type(power_state); 73 74 /* Sanity check the requested suspend levels */ 75 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 76 == PSCI_E_SUCCESS); 77 78 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 79 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 80 ERROR("Invalid target power level for suspend operation\n"); 81 panic(); 82 } 83 84 /* Fast path for CPU standby.*/ 85 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 86 if (psci_plat_pm_ops->cpu_standby == NULL) 87 return PSCI_E_INVALID_PARAMS; 88 89 /* 90 * Set the state of the CPU power domain to the platform 91 * specific retention state and enter the standby state. 92 */ 93 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 94 psci_set_cpu_local_state(cpu_pd_state); 95 96 #if ENABLE_PSCI_STAT 97 plat_psci_stat_accounting_start(&state_info); 98 #endif 99 100 #if ENABLE_RUNTIME_INSTRUMENTATION 101 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 102 RT_INSTR_ENTER_HW_LOW_PWR, 103 PMF_NO_CACHE_MAINT); 104 #endif 105 106 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 107 108 /* Upon exit from standby, set the state back to RUN. */ 109 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 110 111 #if ENABLE_RUNTIME_INSTRUMENTATION 112 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 113 RT_INSTR_EXIT_HW_LOW_PWR, 114 PMF_NO_CACHE_MAINT); 115 #endif 116 117 #if ENABLE_PSCI_STAT 118 plat_psci_stat_accounting_stop(&state_info); 119 120 /* Update PSCI stats */ 121 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); 122 #endif 123 124 return PSCI_E_SUCCESS; 125 } 126 127 /* 128 * If a power down state has been requested, we need to verify entry 129 * point and program entry information. 130 */ 131 if (is_power_down_state != 0U) { 132 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 133 if (rc != PSCI_E_SUCCESS) 134 return rc; 135 } 136 137 /* 138 * Do what is needed to enter the power down state. Upon success, 139 * enter the final wfi which will power down this CPU. This function 140 * might return if the power down was abandoned for any reason, e.g. 141 * arrival of an interrupt 142 */ 143 psci_cpu_suspend_start(&ep, 144 target_pwrlvl, 145 &state_info, 146 is_power_down_state); 147 148 return PSCI_E_SUCCESS; 149 } 150 151 152 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 153 { 154 int rc; 155 psci_power_state_t state_info; 156 entry_point_info_t ep; 157 158 /* Check if the current CPU is the last ON CPU in the system */ 159 if (psci_is_last_on_cpu() == 0U) 160 return PSCI_E_DENIED; 161 162 /* Validate the entry point and get the entry_point_info */ 163 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 164 if (rc != PSCI_E_SUCCESS) 165 return rc; 166 167 /* Query the psci_power_state for system suspend */ 168 psci_query_sys_suspend_pwrstate(&state_info); 169 170 /* 171 * Check if platform allows suspend to Highest power level 172 * (System level) 173 */ 174 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) 175 return PSCI_E_DENIED; 176 177 /* Ensure that the psci_power_state makes sense */ 178 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 179 == PSCI_E_SUCCESS); 180 assert(is_local_state_off( 181 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); 182 183 /* 184 * Do what is needed to enter the system suspend state. This function 185 * might return if the power down was abandoned for any reason, e.g. 186 * arrival of an interrupt 187 */ 188 psci_cpu_suspend_start(&ep, 189 PLAT_MAX_PWR_LVL, 190 &state_info, 191 PSTATE_TYPE_POWERDOWN); 192 193 return PSCI_E_SUCCESS; 194 } 195 196 int psci_cpu_off(void) 197 { 198 int rc; 199 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 200 201 /* 202 * Do what is needed to power off this CPU and possible higher power 203 * levels if it able to do so. Upon success, enter the final wfi 204 * which will power down this CPU. 205 */ 206 rc = psci_do_cpu_off(target_pwrlvl); 207 208 /* 209 * The only error cpu_off can return is E_DENIED. So check if that's 210 * indeed the case. 211 */ 212 assert(rc == PSCI_E_DENIED); 213 214 return rc; 215 } 216 217 int psci_affinity_info(u_register_t target_affinity, 218 unsigned int lowest_affinity_level) 219 { 220 int target_idx; 221 222 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 223 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 224 return PSCI_E_INVALID_PARAMS; 225 226 /* Calculate the cpu index of the target */ 227 target_idx = plat_core_pos_by_mpidr(target_affinity); 228 if (target_idx == -1) 229 return PSCI_E_INVALID_PARAMS; 230 231 /* 232 * Generic management: 233 * Perform cache maintanence ahead of reading the target CPU state to 234 * ensure that the data is not stale. 235 * There is a theoretical edge case where the cache may contain stale 236 * data for the target CPU data - this can occur under the following 237 * conditions: 238 * - the target CPU is in another cluster from the current 239 * - the target CPU was the last CPU to shutdown on its cluster 240 * - the cluster was removed from coherency as part of the CPU shutdown 241 * 242 * In this case the cache maintenace that was performed as part of the 243 * target CPUs shutdown was not seen by the current CPU's cluster. And 244 * so the cache may contain stale data for the target CPU. 245 */ 246 flush_cpu_data_by_index((unsigned int)target_idx, 247 psci_svc_cpu_data.aff_info_state); 248 249 return psci_get_aff_info_state_by_idx(target_idx); 250 } 251 252 int psci_migrate(u_register_t target_cpu) 253 { 254 int rc; 255 u_register_t resident_cpu_mpidr; 256 257 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 258 if (rc != PSCI_TOS_UP_MIG_CAP) 259 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 260 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 261 262 /* 263 * Migrate should only be invoked on the CPU where 264 * the Secure OS is resident. 265 */ 266 if (resident_cpu_mpidr != read_mpidr_el1()) 267 return PSCI_E_NOT_PRESENT; 268 269 /* Check the validity of the specified target cpu */ 270 rc = psci_validate_mpidr(target_cpu); 271 if (rc != PSCI_E_SUCCESS) 272 return PSCI_E_INVALID_PARAMS; 273 274 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); 275 276 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 277 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 278 279 return rc; 280 } 281 282 int psci_migrate_info_type(void) 283 { 284 u_register_t resident_cpu_mpidr; 285 286 return psci_spd_migrate_info(&resident_cpu_mpidr); 287 } 288 289 u_register_t psci_migrate_info_up_cpu(void) 290 { 291 u_register_t resident_cpu_mpidr; 292 int rc; 293 294 /* 295 * Return value of this depends upon what 296 * psci_spd_migrate_info() returns. 297 */ 298 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 299 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP)) 300 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS; 301 302 return resident_cpu_mpidr; 303 } 304 305 int psci_node_hw_state(u_register_t target_cpu, 306 unsigned int power_level) 307 { 308 int rc; 309 310 /* Validate target_cpu */ 311 rc = psci_validate_mpidr(target_cpu); 312 if (rc != PSCI_E_SUCCESS) 313 return PSCI_E_INVALID_PARAMS; 314 315 /* Validate power_level against PLAT_MAX_PWR_LVL */ 316 if (power_level > PLAT_MAX_PWR_LVL) 317 return PSCI_E_INVALID_PARAMS; 318 319 /* 320 * Dispatch this call to platform to query power controller, and pass on 321 * to the caller what it returns 322 */ 323 assert(psci_plat_pm_ops->get_node_hw_state != NULL); 324 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 325 assert(((rc >= HW_ON) && (rc <= HW_STANDBY)) 326 || (rc == PSCI_E_NOT_SUPPORTED) 327 || (rc == PSCI_E_INVALID_PARAMS)); 328 return rc; 329 } 330 331 int psci_features(unsigned int psci_fid) 332 { 333 unsigned int local_caps = psci_caps; 334 335 if (psci_fid == SMCCC_VERSION) 336 return PSCI_E_SUCCESS; 337 338 /* Check if it is a 64 bit function */ 339 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 340 local_caps &= PSCI_CAP_64BIT_MASK; 341 342 /* Check for invalid fid */ 343 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 344 && is_psci_fid(psci_fid))) 345 return PSCI_E_NOT_SUPPORTED; 346 347 348 /* Check if the psci fid is supported or not */ 349 if ((local_caps & define_psci_cap(psci_fid)) == 0U) 350 return PSCI_E_NOT_SUPPORTED; 351 352 /* Format the feature flags */ 353 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) || 354 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) { 355 /* 356 * The trusted firmware does not support OS Initiated Mode. 357 */ 358 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) | 359 (((FF_SUPPORTS_OS_INIT_MODE == 1U) ? 0U : 1U) 360 << FF_MODE_SUPPORT_SHIFT)); 361 return (int) ret; 362 } 363 364 /* Return 0 for all other fid's */ 365 return PSCI_E_SUCCESS; 366 } 367 368 /******************************************************************************* 369 * PSCI top level handler for servicing SMCs. 370 ******************************************************************************/ 371 u_register_t psci_smc_handler(uint32_t smc_fid, 372 u_register_t x1, 373 u_register_t x2, 374 u_register_t x3, 375 u_register_t x4, 376 void *cookie, 377 void *handle, 378 u_register_t flags) 379 { 380 u_register_t ret; 381 382 if (is_caller_secure(flags)) 383 return (u_register_t)SMC_UNK; 384 385 /* Check the fid against the capabilities */ 386 if ((psci_caps & define_psci_cap(smc_fid)) == 0U) 387 return (u_register_t)SMC_UNK; 388 389 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 390 /* 32-bit PSCI function, clear top parameter bits */ 391 392 uint32_t r1 = (uint32_t)x1; 393 uint32_t r2 = (uint32_t)x2; 394 uint32_t r3 = (uint32_t)x3; 395 396 switch (smc_fid) { 397 case PSCI_VERSION: 398 ret = (u_register_t)psci_version(); 399 break; 400 401 case PSCI_CPU_OFF: 402 ret = (u_register_t)psci_cpu_off(); 403 break; 404 405 case PSCI_CPU_SUSPEND_AARCH32: 406 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3); 407 break; 408 409 case PSCI_CPU_ON_AARCH32: 410 ret = (u_register_t)psci_cpu_on(r1, r2, r3); 411 break; 412 413 case PSCI_AFFINITY_INFO_AARCH32: 414 ret = (u_register_t)psci_affinity_info(r1, r2); 415 break; 416 417 case PSCI_MIG_AARCH32: 418 ret = (u_register_t)psci_migrate(r1); 419 break; 420 421 case PSCI_MIG_INFO_TYPE: 422 ret = (u_register_t)psci_migrate_info_type(); 423 break; 424 425 case PSCI_MIG_INFO_UP_CPU_AARCH32: 426 ret = psci_migrate_info_up_cpu(); 427 break; 428 429 case PSCI_NODE_HW_STATE_AARCH32: 430 ret = (u_register_t)psci_node_hw_state(r1, r2); 431 break; 432 433 case PSCI_SYSTEM_SUSPEND_AARCH32: 434 ret = (u_register_t)psci_system_suspend(r1, r2); 435 break; 436 437 case PSCI_SYSTEM_OFF: 438 psci_system_off(); 439 /* We should never return from psci_system_off() */ 440 break; 441 442 case PSCI_SYSTEM_RESET: 443 psci_system_reset(); 444 /* We should never return from psci_system_reset() */ 445 break; 446 447 case PSCI_FEATURES: 448 ret = (u_register_t)psci_features(r1); 449 break; 450 451 #if ENABLE_PSCI_STAT 452 case PSCI_STAT_RESIDENCY_AARCH32: 453 ret = psci_stat_residency(r1, r2); 454 break; 455 456 case PSCI_STAT_COUNT_AARCH32: 457 ret = psci_stat_count(r1, r2); 458 break; 459 #endif 460 case PSCI_MEM_PROTECT: 461 ret = psci_mem_protect(r1); 462 break; 463 464 case PSCI_MEM_CHK_RANGE_AARCH32: 465 ret = psci_mem_chk_range(r1, r2); 466 break; 467 468 case PSCI_SYSTEM_RESET2_AARCH32: 469 /* We should never return from psci_system_reset2() */ 470 ret = psci_system_reset2(r1, r2); 471 break; 472 473 default: 474 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 475 ret = (u_register_t)SMC_UNK; 476 break; 477 } 478 } else { 479 /* 64-bit PSCI function */ 480 481 switch (smc_fid) { 482 case PSCI_CPU_SUSPEND_AARCH64: 483 ret = (u_register_t) 484 psci_cpu_suspend((unsigned int)x1, x2, x3); 485 break; 486 487 case PSCI_CPU_ON_AARCH64: 488 ret = (u_register_t)psci_cpu_on(x1, x2, x3); 489 break; 490 491 case PSCI_AFFINITY_INFO_AARCH64: 492 ret = (u_register_t) 493 psci_affinity_info(x1, (unsigned int)x2); 494 break; 495 496 case PSCI_MIG_AARCH64: 497 ret = (u_register_t)psci_migrate(x1); 498 break; 499 500 case PSCI_MIG_INFO_UP_CPU_AARCH64: 501 ret = psci_migrate_info_up_cpu(); 502 break; 503 504 case PSCI_NODE_HW_STATE_AARCH64: 505 ret = (u_register_t)psci_node_hw_state( 506 x1, (unsigned int) x2); 507 break; 508 509 case PSCI_SYSTEM_SUSPEND_AARCH64: 510 ret = (u_register_t)psci_system_suspend(x1, x2); 511 break; 512 513 #if ENABLE_PSCI_STAT 514 case PSCI_STAT_RESIDENCY_AARCH64: 515 ret = psci_stat_residency(x1, (unsigned int) x2); 516 break; 517 518 case PSCI_STAT_COUNT_AARCH64: 519 ret = psci_stat_count(x1, (unsigned int) x2); 520 break; 521 #endif 522 523 case PSCI_MEM_CHK_RANGE_AARCH64: 524 ret = psci_mem_chk_range(x1, x2); 525 break; 526 527 case PSCI_SYSTEM_RESET2_AARCH64: 528 /* We should never return from psci_system_reset2() */ 529 ret = psci_system_reset2((uint32_t) x1, x2); 530 break; 531 532 default: 533 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 534 ret = (u_register_t)SMC_UNK; 535 break; 536 } 537 } 538 539 return ret; 540 } 541