1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cpu_macros.S> 10#include <lib/psci/psci.h> 11#include <platform_def.h> 12 13 .globl psci_do_pwrdown_cache_maintenance 14 .globl psci_do_pwrup_cache_maintenance 15 16/* ----------------------------------------------------------------------- 17 * void psci_do_pwrdown_cache_maintenance(void); 18 * 19 * This function turns off data caches and also ensures that stack memory 20 * is correctly flushed out to avoid coherency issues due to a change in 21 * its memory attributes. 22 * ----------------------------------------------------------------------- 23 */ 24func psci_do_pwrdown_cache_maintenance 25 stp x29, x30, [sp,#-16]! 26 stp x19, x20, [sp,#-16]! 27 28 /* Disable L1 data cache and unified L2 cache */ 29 mrs x1, sctlr_el3 30 bic x1, x1, #SCTLR_C_BIT 31 msr sctlr_el3, x1 32 isb 33 34 /* --------------------------------------------- 35 * Do stack maintenance by flushing the used 36 * stack to the main memory and invalidating the 37 * remainder. 38 * --------------------------------------------- 39 */ 40 bl plat_get_my_stack 41 42 /* --------------------------------------------- 43 * Calculate and store the size of the used 44 * stack memory in x1. 45 * --------------------------------------------- 46 */ 47 mov x19, x0 48 mov x1, sp 49 sub x1, x0, x1 50 mov x0, sp 51 bl flush_dcache_range 52 53 /* --------------------------------------------- 54 * Calculate and store the size of the unused 55 * stack memory in x1. Calculate and store the 56 * stack base address in x0. 57 * --------------------------------------------- 58 */ 59 sub x0, x19, #PLATFORM_STACK_SIZE 60 sub x1, sp, x0 61 bl inv_dcache_range 62 63 ldp x19, x20, [sp], #16 64 ldp x29, x30, [sp], #16 65 ret 66endfunc psci_do_pwrdown_cache_maintenance 67 68 69/* ----------------------------------------------------------------------- 70 * void psci_do_pwrup_cache_maintenance(void); 71 * 72 * This function performs cache maintenance after this cpu is powered up. 73 * Currently, this involves managing the used stack memory before turning 74 * on the data cache. 75 * ----------------------------------------------------------------------- 76 */ 77func psci_do_pwrup_cache_maintenance 78 stp x29, x30, [sp,#-16]! 79 80 /* --------------------------------------------- 81 * Ensure any inflight stack writes have made it 82 * to main memory. 83 * --------------------------------------------- 84 */ 85 dmb st 86 87 /* --------------------------------------------- 88 * Calculate and store the size of the used 89 * stack memory in x1. Calculate and store the 90 * stack base address in x0. 91 * --------------------------------------------- 92 */ 93 bl plat_get_my_stack 94 mov x1, sp 95 sub x1, x0, x1 96 mov x0, sp 97 bl inv_dcache_range 98 99 /* --------------------------------------------- 100 * Enable the data cache. 101 * --------------------------------------------- 102 */ 103 mrs x0, sctlr_el3 104 orr x0, x0, #SCTLR_C_BIT 105 msr sctlr_el3, x0 106 isb 107 108 ldp x29, x30, [sp], #16 109 ret 110endfunc psci_do_pwrup_cache_maintenance 111