1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <platform_def.h> 34#include <psci.h> 35 36 .globl psci_do_pwrdown_cache_maintenance 37 .globl psci_do_pwrup_cache_maintenance 38 39/* ----------------------------------------------------------------------- 40 * void psci_do_pwrdown_cache_maintenance(unsigned int power level); 41 * 42 * This function performs cache maintenance for the specified power 43 * level. The levels of cache affected are determined by the power 44 * level which is passed as the argument i.e. level 0 results 45 * in a flush of the L1 cache. Both the L1 and L2 caches are flushed 46 * for a higher power level. 47 * 48 * Additionally, this function also ensures that stack memory is correctly 49 * flushed out to avoid coherency issues due to a change in its memory 50 * attributes after the data cache is disabled. 51 * ----------------------------------------------------------------------- 52 */ 53func psci_do_pwrdown_cache_maintenance 54 stp x29, x30, [sp,#-16]! 55 stp x19, x20, [sp,#-16]! 56 57 /* --------------------------------------------- 58 * Determine to how many levels of cache will be 59 * subject to cache maintenance. Power level 60 * 0 implies that only the cpu is being powered 61 * down. Only the L1 data cache needs to be 62 * flushed to the PoU in this case. For a higher 63 * power level we are assuming that a flush 64 * of L1 data and L2 unified cache is enough. 65 * This information should be provided by the 66 * platform. 67 * --------------------------------------------- 68 */ 69 cmp w0, #PSCI_CPU_PWR_LVL 70 b.eq do_core_pwr_dwn 71 bl prepare_cluster_pwr_dwn 72 b do_stack_maintenance 73 74do_core_pwr_dwn: 75 bl prepare_core_pwr_dwn 76 77 /* --------------------------------------------- 78 * Do stack maintenance by flushing the used 79 * stack to the main memory and invalidating the 80 * remainder. 81 * --------------------------------------------- 82 */ 83do_stack_maintenance: 84 bl plat_get_my_stack 85 86 /* --------------------------------------------- 87 * Calculate and store the size of the used 88 * stack memory in x1. 89 * --------------------------------------------- 90 */ 91 mov x19, x0 92 mov x1, sp 93 sub x1, x0, x1 94 mov x0, sp 95 bl flush_dcache_range 96 97 /* --------------------------------------------- 98 * Calculate and store the size of the unused 99 * stack memory in x1. Calculate and store the 100 * stack base address in x0. 101 * --------------------------------------------- 102 */ 103 sub x0, x19, #PLATFORM_STACK_SIZE 104 sub x1, sp, x0 105 bl inv_dcache_range 106 107 ldp x19, x20, [sp], #16 108 ldp x29, x30, [sp], #16 109 ret 110endfunc psci_do_pwrdown_cache_maintenance 111 112 113/* ----------------------------------------------------------------------- 114 * void psci_do_pwrup_cache_maintenance(void); 115 * 116 * This function performs cache maintenance after this cpu is powered up. 117 * Currently, this involves managing the used stack memory before turning 118 * on the data cache. 119 * ----------------------------------------------------------------------- 120 */ 121func psci_do_pwrup_cache_maintenance 122 stp x29, x30, [sp,#-16]! 123 124 /* --------------------------------------------- 125 * Ensure any inflight stack writes have made it 126 * to main memory. 127 * --------------------------------------------- 128 */ 129 dmb st 130 131 /* --------------------------------------------- 132 * Calculate and store the size of the used 133 * stack memory in x1. Calculate and store the 134 * stack base address in x0. 135 * --------------------------------------------- 136 */ 137 bl plat_get_my_stack 138 mov x1, sp 139 sub x1, x0, x1 140 mov x0, sp 141 bl inv_dcache_range 142 143 /* --------------------------------------------- 144 * Enable the data cache. 145 * --------------------------------------------- 146 */ 147 mrs x0, sctlr_el3 148 orr x0, x0, #SCTLR_C_BIT 149 msr sctlr_el3, x0 150 isb 151 152 ldp x29, x30, [sp], #16 153 ret 154endfunc psci_do_pwrup_cache_maintenance 155