1 /* 2 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/el3_runtime/context_mgmt.h> 14 #include <lib/extensions/sme.h> 15 #include <lib/extensions/sve.h> 16 17 void sme_enable(cpu_context_t *context) 18 { 19 u_register_t reg; 20 el3_state_t *state; 21 22 /* Get the context state. */ 23 state = get_el3state_ctx(context); 24 25 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 26 reg = read_ctx_reg(state, CTX_SCR_EL3); 27 reg |= SCR_ENTP2_BIT; 28 write_ctx_reg(state, CTX_SCR_EL3, reg); 29 } 30 31 void sme_enable_per_world(per_world_context_t *per_world_ctx) 32 { 33 u_register_t reg; 34 35 /* Enable SME in CPTR_EL3. */ 36 reg = per_world_ctx->ctx_cptr_el3; 37 reg |= ESM_BIT; 38 per_world_ctx->ctx_cptr_el3 = reg; 39 } 40 41 void sme_init_el3(void) 42 { 43 u_register_t cptr_el3 = read_cptr_el3(); 44 u_register_t smcr_el3; 45 46 /* Set CPTR_EL3.ESM bit so we can access SMCR_EL3 without trapping. */ 47 write_cptr_el3(cptr_el3 | ESM_BIT); 48 isb(); 49 50 /* 51 * Set the max LEN value and FA64 bit. This register is set up per_world 52 * to be the least restrictive, then lower ELs can restrict as needed 53 * using SMCR_EL2 and SMCR_EL1. 54 */ 55 smcr_el3 = SMCR_ELX_LEN_MAX; 56 if (read_feat_sme_fa64_id_field() != 0U) { 57 VERBOSE("[SME] FA64 enabled\n"); 58 smcr_el3 |= SMCR_ELX_FA64_BIT; 59 } 60 61 /* 62 * Enable access to ZT0 register. 63 * Make sure FEAT_SME2 is supported by the hardware before continuing. 64 * If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to 65 * access ZT0 register without trapping. 66 */ 67 if (is_feat_sme2_supported()) { 68 VERBOSE("SME2 enabled\n"); 69 smcr_el3 |= SMCR_ELX_EZT0_BIT; 70 } 71 write_smcr_el3(smcr_el3); 72 73 /* Reset CPTR_EL3 value. */ 74 write_cptr_el3(cptr_el3); 75 isb(); 76 } 77 78 void sme_init_el2_unused(void) 79 { 80 /* 81 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 accesses to the 82 * CPACR_EL1 or CPACR from both Execution states do not trap to EL2. 83 */ 84 write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TCPAC_BIT); 85 } 86 87 void sme_disable(cpu_context_t *context) 88 { 89 u_register_t reg; 90 el3_state_t *state; 91 92 /* Get the context state. */ 93 state = get_el3state_ctx(context); 94 95 /* Disable access to TPIDR2_EL0. */ 96 reg = read_ctx_reg(state, CTX_SCR_EL3); 97 reg &= ~SCR_ENTP2_BIT; 98 write_ctx_reg(state, CTX_SCR_EL3, reg); 99 } 100 101 void sme_disable_per_world(per_world_context_t *per_world_ctx) 102 { 103 u_register_t reg; 104 105 /* Disable SME, SVE, and FPU since they all share registers. */ 106 reg = per_world_ctx->ctx_cptr_el3; 107 reg &= ~ESM_BIT; /* Trap SME */ 108 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 109 reg |= TFP_BIT; /* Trap FPU/SIMD */ 110 per_world_ctx->ctx_cptr_el3 = reg; 111 } 112