1dc78e62dSjohpow01 /* 226a3351eSMark Brown * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. 3dc78e62dSjohpow01 * 4dc78e62dSjohpow01 * SPDX-License-Identifier: BSD-3-Clause 5dc78e62dSjohpow01 */ 6dc78e62dSjohpow01 7dc78e62dSjohpow01 #include <stdbool.h> 8dc78e62dSjohpow01 9dc78e62dSjohpow01 #include <arch.h> 10dc78e62dSjohpow01 #include <arch_helpers.h> 11dc78e62dSjohpow01 #include <common/debug.h> 12dc78e62dSjohpow01 #include <lib/el3_runtime/context_mgmt.h> 13dc78e62dSjohpow01 #include <lib/extensions/sme.h> 14dc78e62dSjohpow01 #include <lib/extensions/sve.h> 15dc78e62dSjohpow01 16dc78e62dSjohpow01 static bool feat_sme_supported(void) 17dc78e62dSjohpow01 { 18dc78e62dSjohpow01 uint64_t features; 19dc78e62dSjohpow01 20dc78e62dSjohpow01 features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT; 21dc78e62dSjohpow01 return (features & ID_AA64PFR1_EL1_SME_MASK) != 0U; 22dc78e62dSjohpow01 } 23dc78e62dSjohpow01 24dc78e62dSjohpow01 static bool feat_sme_fa64_supported(void) 25dc78e62dSjohpow01 { 26dc78e62dSjohpow01 uint64_t features; 27dc78e62dSjohpow01 28dc78e62dSjohpow01 features = read_id_aa64smfr0_el1(); 29dc78e62dSjohpow01 return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U; 30dc78e62dSjohpow01 } 31dc78e62dSjohpow01 32dc78e62dSjohpow01 void sme_enable(cpu_context_t *context) 33dc78e62dSjohpow01 { 34dc78e62dSjohpow01 u_register_t reg; 35dc78e62dSjohpow01 u_register_t cptr_el3; 36dc78e62dSjohpow01 el3_state_t *state; 37dc78e62dSjohpow01 38dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 39dc78e62dSjohpow01 if (!feat_sme_supported()) { 4026a3351eSMark Brown /* Perhaps the hardware supports SVE only */ 4126a3351eSMark Brown sve_enable(context); 42dc78e62dSjohpow01 return; 43dc78e62dSjohpow01 } 44dc78e62dSjohpow01 45dc78e62dSjohpow01 /* Get the context state. */ 46dc78e62dSjohpow01 state = get_el3state_ctx(context); 47dc78e62dSjohpow01 48dc78e62dSjohpow01 /* Enable SME in CPTR_EL3. */ 49dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 50dc78e62dSjohpow01 reg |= ESM_BIT; 51dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 52dc78e62dSjohpow01 53dc78e62dSjohpow01 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 54dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_SCR_EL3); 55dc78e62dSjohpow01 reg |= SCR_ENTP2_BIT; 56dc78e62dSjohpow01 write_ctx_reg(state, CTX_SCR_EL3, reg); 57dc78e62dSjohpow01 58dc78e62dSjohpow01 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ 59dc78e62dSjohpow01 cptr_el3 = read_cptr_el3(); 60dc78e62dSjohpow01 write_cptr_el3(cptr_el3 | ESM_BIT); 61*46e92f28SBoyan Karatotev isb(); 62dc78e62dSjohpow01 63dc78e62dSjohpow01 /* 64dc78e62dSjohpow01 * Set the max LEN value and FA64 bit. This register is set up globally 65dc78e62dSjohpow01 * to be the least restrictive, then lower ELs can restrict as needed 66dc78e62dSjohpow01 * using SMCR_EL2 and SMCR_EL1. 67dc78e62dSjohpow01 */ 68dc78e62dSjohpow01 reg = SMCR_ELX_LEN_MASK; 69dc78e62dSjohpow01 if (feat_sme_fa64_supported()) { 70dc78e62dSjohpow01 VERBOSE("[SME] FA64 enabled\n"); 71dc78e62dSjohpow01 reg |= SMCR_ELX_FA64_BIT; 72dc78e62dSjohpow01 } 73dc78e62dSjohpow01 write_smcr_el3(reg); 74dc78e62dSjohpow01 75dc78e62dSjohpow01 /* Reset CPTR_EL3 value. */ 76dc78e62dSjohpow01 write_cptr_el3(cptr_el3); 77*46e92f28SBoyan Karatotev isb(); 78dc78e62dSjohpow01 79dc78e62dSjohpow01 /* Enable SVE/FPU in addition to SME. */ 80dc78e62dSjohpow01 sve_enable(context); 81dc78e62dSjohpow01 } 82dc78e62dSjohpow01 83dc78e62dSjohpow01 void sme_disable(cpu_context_t *context) 84dc78e62dSjohpow01 { 85dc78e62dSjohpow01 u_register_t reg; 86dc78e62dSjohpow01 el3_state_t *state; 87dc78e62dSjohpow01 88dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 89dc78e62dSjohpow01 if (!feat_sme_supported()) { 9026a3351eSMark Brown /* Perhaps the hardware supports SVE only */ 9126a3351eSMark Brown sve_disable(context); 92dc78e62dSjohpow01 return; 93dc78e62dSjohpow01 } 94dc78e62dSjohpow01 95dc78e62dSjohpow01 /* Get the context state. */ 96dc78e62dSjohpow01 state = get_el3state_ctx(context); 97dc78e62dSjohpow01 98dc78e62dSjohpow01 /* Disable SME, SVE, and FPU since they all share registers. */ 99dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 100dc78e62dSjohpow01 reg &= ~ESM_BIT; /* Trap SME */ 101dc78e62dSjohpow01 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 102dc78e62dSjohpow01 reg |= TFP_BIT; /* Trap FPU/SIMD */ 103dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 104dc78e62dSjohpow01 105dc78e62dSjohpow01 /* Disable access to TPIDR2_EL0. */ 106dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_SCR_EL3); 107dc78e62dSjohpow01 reg &= ~SCR_ENTP2_BIT; 108dc78e62dSjohpow01 write_ctx_reg(state, CTX_SCR_EL3, reg); 109dc78e62dSjohpow01 } 110