1dc78e62dSjohpow01 /* 2*45007acdSJayanth Dodderi Chidanand * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. 3dc78e62dSjohpow01 * 4dc78e62dSjohpow01 * SPDX-License-Identifier: BSD-3-Clause 5dc78e62dSjohpow01 */ 6dc78e62dSjohpow01 7dc78e62dSjohpow01 #include <stdbool.h> 8dc78e62dSjohpow01 9dc78e62dSjohpow01 #include <arch.h> 10*45007acdSJayanth Dodderi Chidanand #include <arch_features.h> 11dc78e62dSjohpow01 #include <arch_helpers.h> 12dc78e62dSjohpow01 #include <common/debug.h> 13dc78e62dSjohpow01 #include <lib/el3_runtime/context_mgmt.h> 14dc78e62dSjohpow01 #include <lib/extensions/sme.h> 15dc78e62dSjohpow01 #include <lib/extensions/sve.h> 16dc78e62dSjohpow01 17dc78e62dSjohpow01 void sme_enable(cpu_context_t *context) 18dc78e62dSjohpow01 { 19dc78e62dSjohpow01 u_register_t reg; 20dc78e62dSjohpow01 u_register_t cptr_el3; 21dc78e62dSjohpow01 el3_state_t *state; 22dc78e62dSjohpow01 23dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 24*45007acdSJayanth Dodderi Chidanand if (!is_feat_sme_supported()) { 2526a3351eSMark Brown /* Perhaps the hardware supports SVE only */ 2626a3351eSMark Brown sve_enable(context); 27dc78e62dSjohpow01 return; 28dc78e62dSjohpow01 } 29dc78e62dSjohpow01 30dc78e62dSjohpow01 /* Get the context state. */ 31dc78e62dSjohpow01 state = get_el3state_ctx(context); 32dc78e62dSjohpow01 33dc78e62dSjohpow01 /* Enable SME in CPTR_EL3. */ 34dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 35dc78e62dSjohpow01 reg |= ESM_BIT; 36dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 37dc78e62dSjohpow01 38dc78e62dSjohpow01 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 39dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_SCR_EL3); 40dc78e62dSjohpow01 reg |= SCR_ENTP2_BIT; 41dc78e62dSjohpow01 write_ctx_reg(state, CTX_SCR_EL3, reg); 42dc78e62dSjohpow01 43dc78e62dSjohpow01 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ 44dc78e62dSjohpow01 cptr_el3 = read_cptr_el3(); 45dc78e62dSjohpow01 write_cptr_el3(cptr_el3 | ESM_BIT); 4646e92f28SBoyan Karatotev isb(); 47dc78e62dSjohpow01 48dc78e62dSjohpow01 /* 49dc78e62dSjohpow01 * Set the max LEN value and FA64 bit. This register is set up globally 50dc78e62dSjohpow01 * to be the least restrictive, then lower ELs can restrict as needed 51dc78e62dSjohpow01 * using SMCR_EL2 and SMCR_EL1. 52dc78e62dSjohpow01 */ 53dc78e62dSjohpow01 reg = SMCR_ELX_LEN_MASK; 54*45007acdSJayanth Dodderi Chidanand if (read_feat_sme_fa64_id_field() != 0U) { 55dc78e62dSjohpow01 VERBOSE("[SME] FA64 enabled\n"); 56dc78e62dSjohpow01 reg |= SMCR_ELX_FA64_BIT; 57dc78e62dSjohpow01 } 58dc78e62dSjohpow01 write_smcr_el3(reg); 59dc78e62dSjohpow01 60dc78e62dSjohpow01 /* Reset CPTR_EL3 value. */ 61dc78e62dSjohpow01 write_cptr_el3(cptr_el3); 6246e92f28SBoyan Karatotev isb(); 63dc78e62dSjohpow01 64dc78e62dSjohpow01 /* Enable SVE/FPU in addition to SME. */ 65dc78e62dSjohpow01 sve_enable(context); 66dc78e62dSjohpow01 } 67dc78e62dSjohpow01 68dc78e62dSjohpow01 void sme_disable(cpu_context_t *context) 69dc78e62dSjohpow01 { 70dc78e62dSjohpow01 u_register_t reg; 71dc78e62dSjohpow01 el3_state_t *state; 72dc78e62dSjohpow01 73dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 74*45007acdSJayanth Dodderi Chidanand if (!is_feat_sme_supported()) { 7526a3351eSMark Brown /* Perhaps the hardware supports SVE only */ 7626a3351eSMark Brown sve_disable(context); 77dc78e62dSjohpow01 return; 78dc78e62dSjohpow01 } 79dc78e62dSjohpow01 80dc78e62dSjohpow01 /* Get the context state. */ 81dc78e62dSjohpow01 state = get_el3state_ctx(context); 82dc78e62dSjohpow01 83dc78e62dSjohpow01 /* Disable SME, SVE, and FPU since they all share registers. */ 84dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 85dc78e62dSjohpow01 reg &= ~ESM_BIT; /* Trap SME */ 86dc78e62dSjohpow01 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 87dc78e62dSjohpow01 reg |= TFP_BIT; /* Trap FPU/SIMD */ 88dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 89dc78e62dSjohpow01 90dc78e62dSjohpow01 /* Disable access to TPIDR2_EL0. */ 91dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_SCR_EL3); 92dc78e62dSjohpow01 reg &= ~SCR_ENTP2_BIT; 93dc78e62dSjohpow01 write_ctx_reg(state, CTX_SCR_EL3, reg); 94dc78e62dSjohpow01 } 95