1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <bl31/interrupt_mgmt.h> 16 #include <common/bl_common.h> 17 #include <context.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/el3_runtime/pubsub_events.h> 20 #include <lib/extensions/amu.h> 21 #include <lib/extensions/mpam.h> 22 #include <lib/extensions/spe.h> 23 #include <lib/extensions/sve.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 #include <smccc_helpers.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 uint32_t scr_el3, pmcr_el0; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 unsigned long sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = (uint32_t)read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 if (security_state == NON_SECURE) 136 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 137 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 138 139 #ifdef IMAGE_BL31 140 /* 141 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 142 * indicated by the interrupt routing model for BL31. 143 */ 144 scr_el3 |= get_scr_el3_from_routing_model(security_state); 145 #endif 146 147 /* 148 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 149 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 150 * next mode is Hyp. 151 */ 152 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 153 || ((GET_RW(ep->spsr) != MODE_RW_64) 154 && (GET_M32(ep->spsr) == MODE32_hyp))) { 155 scr_el3 |= SCR_HCE_BIT; 156 } 157 158 /* 159 * Initialise SCTLR_EL1 to the reset value corresponding to the target 160 * execution state setting all fields rather than relying of the hw. 161 * Some fields have architecturally UNKNOWN reset values and these are 162 * set to zero. 163 * 164 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 165 * 166 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 167 * required by PSCI specification) 168 */ 169 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 170 if (GET_RW(ep->spsr) == MODE_RW_64) 171 sctlr_elx |= SCTLR_EL1_RES1; 172 else { 173 /* 174 * If the target execution state is AArch32 then the following 175 * fields need to be set. 176 * 177 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 178 * instructions are not trapped to EL1. 179 * 180 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 181 * instructions are not trapped to EL1. 182 * 183 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 184 * CP15DMB, CP15DSB, and CP15ISB instructions. 185 */ 186 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 187 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 188 } 189 190 #if ERRATA_A75_764081 191 /* 192 * If workaround of errata 764081 for Cortex-A75 is used then set 193 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 194 */ 195 sctlr_elx |= SCTLR_IESB_BIT; 196 #endif 197 198 /* 199 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 200 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 201 * are not part of the stored cpu_context. 202 */ 203 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 204 205 /* 206 * Base the context ACTLR_EL1 on the current value, as it is 207 * implementation defined. The context restore process will write 208 * the value from the context to the actual register and can cause 209 * problems for processor cores that don't expect certain bits to 210 * be zero. 211 */ 212 actlr_elx = read_actlr_el1(); 213 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 214 215 if (security_state == SECURE) { 216 /* 217 * Initialise PMCR_EL0 for secure context only, setting all 218 * fields rather than relying on hw. Some fields are 219 * architecturally UNKNOWN on reset. 220 * 221 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 222 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 223 * that changes PMCCNTR_EL0[63] from 1 to 0. 224 * 225 * PMCR_EL0.DP: Set to one so that the cycle counter, 226 * PMCCNTR_EL0 does not count when event counting is prohibited. 227 * 228 * PMCR_EL0.X: Set to zero to disable export of events. 229 * 230 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 231 * counts on every clock cycle. 232 */ 233 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 234 | PMCR_EL0_DP_BIT) 235 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 236 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 237 } 238 239 /* Populate EL3 state so that we've the right context before doing ERET */ 240 state = get_el3state_ctx(ctx); 241 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 242 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 243 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 244 245 /* 246 * Store the X0-X7 value from the entrypoint into the context 247 * Use memcpy as we are in control of the layout of the structures 248 */ 249 gp_regs = get_gpregs_ctx(ctx); 250 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 251 } 252 253 /******************************************************************************* 254 * Enable architecture extensions on first entry to Non-secure world. 255 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 256 * it is zero. 257 ******************************************************************************/ 258 static void enable_extensions_nonsecure(bool el2_unused) 259 { 260 #if IMAGE_BL31 261 #if ENABLE_SPE_FOR_LOWER_ELS 262 spe_enable(el2_unused); 263 #endif 264 265 #if ENABLE_AMU 266 amu_enable(el2_unused); 267 #endif 268 269 #if ENABLE_SVE_FOR_NS 270 sve_enable(el2_unused); 271 #endif 272 273 #if ENABLE_MPAM_FOR_LOWER_ELS 274 mpam_enable(el2_unused); 275 #endif 276 #endif 277 } 278 279 /******************************************************************************* 280 * The following function initializes the cpu_context for a CPU specified by 281 * its `cpu_idx` for first use, and sets the initial entrypoint state as 282 * specified by the entry_point_info structure. 283 ******************************************************************************/ 284 void cm_init_context_by_index(unsigned int cpu_idx, 285 const entry_point_info_t *ep) 286 { 287 cpu_context_t *ctx; 288 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 289 cm_setup_context(ctx, ep); 290 } 291 292 /******************************************************************************* 293 * The following function initializes the cpu_context for the current CPU 294 * for first use, and sets the initial entrypoint state as specified by the 295 * entry_point_info structure. 296 ******************************************************************************/ 297 void cm_init_my_context(const entry_point_info_t *ep) 298 { 299 cpu_context_t *ctx; 300 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 301 cm_setup_context(ctx, ep); 302 } 303 304 /******************************************************************************* 305 * Prepare the CPU system registers for first entry into secure or normal world 306 * 307 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 308 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 309 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 310 * For all entries, the EL1 registers are initialized from the cpu_context 311 ******************************************************************************/ 312 void cm_prepare_el3_exit(uint32_t security_state) 313 { 314 uint32_t sctlr_elx, scr_el3, mdcr_el2; 315 cpu_context_t *ctx = cm_get_context(security_state); 316 bool el2_unused = false; 317 uint64_t hcr_el2 = 0U; 318 319 assert(ctx != NULL); 320 321 if (security_state == NON_SECURE) { 322 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 323 CTX_SCR_EL3); 324 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 325 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 326 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 327 CTX_SCTLR_EL1); 328 sctlr_elx &= SCTLR_EE_BIT; 329 sctlr_elx |= SCTLR_EL2_RES1; 330 #if ERRATA_A75_764081 331 /* 332 * If workaround of errata 764081 for Cortex-A75 is used 333 * then set SCTLR_EL2.IESB to enable Implicit Error 334 * Synchronization Barrier. 335 */ 336 sctlr_elx |= SCTLR_IESB_BIT; 337 #endif 338 write_sctlr_el2(sctlr_elx); 339 } else if (el_implemented(2) != EL_IMPL_NONE) { 340 el2_unused = true; 341 342 /* 343 * EL2 present but unused, need to disable safely. 344 * SCTLR_EL2 can be ignored in this case. 345 * 346 * Set EL2 register width appropriately: Set HCR_EL2 347 * field to match SCR_EL3.RW. 348 */ 349 if ((scr_el3 & SCR_RW_BIT) != 0U) 350 hcr_el2 |= HCR_RW_BIT; 351 352 /* 353 * For Armv8.3 pointer authentication feature, disable 354 * traps to EL2 when accessing key registers or using 355 * pointer authentication instructions from lower ELs. 356 */ 357 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 358 359 write_hcr_el2(hcr_el2); 360 361 /* 362 * Initialise CPTR_EL2 setting all fields rather than 363 * relying on the hw. All fields have architecturally 364 * UNKNOWN reset values. 365 * 366 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 367 * accesses to the CPACR_EL1 or CPACR from both 368 * Execution states do not trap to EL2. 369 * 370 * CPTR_EL2.TTA: Set to zero so that Non-secure System 371 * register accesses to the trace registers from both 372 * Execution states do not trap to EL2. 373 * 374 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 375 * to SIMD and floating-point functionality from both 376 * Execution states do not trap to EL2. 377 */ 378 write_cptr_el2(CPTR_EL2_RESET_VAL & 379 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 380 | CPTR_EL2_TFP_BIT)); 381 382 /* 383 * Initialise CNTHCTL_EL2. All fields are 384 * architecturally UNKNOWN on reset and are set to zero 385 * except for field(s) listed below. 386 * 387 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 388 * Hyp mode of Non-secure EL0 and EL1 accesses to the 389 * physical timer registers. 390 * 391 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 392 * Hyp mode of Non-secure EL0 and EL1 accesses to the 393 * physical counter registers. 394 */ 395 write_cnthctl_el2(CNTHCTL_RESET_VAL | 396 EL1PCEN_BIT | EL1PCTEN_BIT); 397 398 /* 399 * Initialise CNTVOFF_EL2 to zero as it resets to an 400 * architecturally UNKNOWN value. 401 */ 402 write_cntvoff_el2(0); 403 404 /* 405 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 406 * MPIDR_EL1 respectively. 407 */ 408 write_vpidr_el2(read_midr_el1()); 409 write_vmpidr_el2(read_mpidr_el1()); 410 411 /* 412 * Initialise VTTBR_EL2. All fields are architecturally 413 * UNKNOWN on reset. 414 * 415 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 416 * 2 address translation is disabled, cache maintenance 417 * operations depend on the VMID. 418 * 419 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 420 * translation is disabled. 421 */ 422 write_vttbr_el2(VTTBR_RESET_VAL & 423 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 424 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 425 426 /* 427 * Initialise MDCR_EL2, setting all fields rather than 428 * relying on hw. Some fields are architecturally 429 * UNKNOWN on reset. 430 * 431 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 432 * EL1 System register accesses to the Debug ROM 433 * registers are not trapped to EL2. 434 * 435 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 436 * System register accesses to the powerdown debug 437 * registers are not trapped to EL2. 438 * 439 * MDCR_EL2.TDA: Set to zero so that System register 440 * accesses to the debug registers do not trap to EL2. 441 * 442 * MDCR_EL2.TDE: Set to zero so that debug exceptions 443 * are not routed to EL2. 444 * 445 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 446 * Monitors. 447 * 448 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 449 * EL1 accesses to all Performance Monitors registers 450 * are not trapped to EL2. 451 * 452 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 453 * and EL1 accesses to the PMCR_EL0 or PMCR are not 454 * trapped to EL2. 455 * 456 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 457 * architecturally-defined reset value. 458 */ 459 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 460 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 461 >> PMCR_EL0_N_SHIFT)) & 462 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 463 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 464 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 465 | MDCR_EL2_TPMCR_BIT)); 466 467 write_mdcr_el2(mdcr_el2); 468 469 /* 470 * Initialise HSTR_EL2. All fields are architecturally 471 * UNKNOWN on reset. 472 * 473 * HSTR_EL2.T<n>: Set all these fields to zero so that 474 * Non-secure EL0 or EL1 accesses to System registers 475 * do not trap to EL2. 476 */ 477 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 478 /* 479 * Initialise CNTHP_CTL_EL2. All fields are 480 * architecturally UNKNOWN on reset. 481 * 482 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 483 * physical timer and prevent timer interrupts. 484 */ 485 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 486 ~(CNTHP_CTL_ENABLE_BIT)); 487 } 488 enable_extensions_nonsecure(el2_unused); 489 } 490 491 cm_el1_sysregs_context_restore(security_state); 492 cm_set_next_eret_context(security_state); 493 } 494 495 /******************************************************************************* 496 * The next four functions are used by runtime services to save and restore 497 * EL1 context on the 'cpu_context' structure for the specified security 498 * state. 499 ******************************************************************************/ 500 void cm_el1_sysregs_context_save(uint32_t security_state) 501 { 502 cpu_context_t *ctx; 503 504 ctx = cm_get_context(security_state); 505 assert(ctx != NULL); 506 507 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 508 509 #if IMAGE_BL31 510 if (security_state == SECURE) 511 PUBLISH_EVENT(cm_exited_secure_world); 512 else 513 PUBLISH_EVENT(cm_exited_normal_world); 514 #endif 515 } 516 517 void cm_el1_sysregs_context_restore(uint32_t security_state) 518 { 519 cpu_context_t *ctx; 520 521 ctx = cm_get_context(security_state); 522 assert(ctx != NULL); 523 524 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 525 526 #if IMAGE_BL31 527 if (security_state == SECURE) 528 PUBLISH_EVENT(cm_entering_secure_world); 529 else 530 PUBLISH_EVENT(cm_entering_normal_world); 531 #endif 532 } 533 534 /******************************************************************************* 535 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 536 * given security state with the given entrypoint 537 ******************************************************************************/ 538 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 539 { 540 cpu_context_t *ctx; 541 el3_state_t *state; 542 543 ctx = cm_get_context(security_state); 544 assert(ctx != NULL); 545 546 /* Populate EL3 state so that ERET jumps to the correct entry */ 547 state = get_el3state_ctx(ctx); 548 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 549 } 550 551 /******************************************************************************* 552 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 553 * pertaining to the given security state 554 ******************************************************************************/ 555 void cm_set_elr_spsr_el3(uint32_t security_state, 556 uintptr_t entrypoint, uint32_t spsr) 557 { 558 cpu_context_t *ctx; 559 el3_state_t *state; 560 561 ctx = cm_get_context(security_state); 562 assert(ctx != NULL); 563 564 /* Populate EL3 state so that ERET jumps to the correct entry */ 565 state = get_el3state_ctx(ctx); 566 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 567 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 568 } 569 570 /******************************************************************************* 571 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 572 * pertaining to the given security state using the value and bit position 573 * specified in the parameters. It preserves all other bits. 574 ******************************************************************************/ 575 void cm_write_scr_el3_bit(uint32_t security_state, 576 uint32_t bit_pos, 577 uint32_t value) 578 { 579 cpu_context_t *ctx; 580 el3_state_t *state; 581 uint32_t scr_el3; 582 583 ctx = cm_get_context(security_state); 584 assert(ctx != NULL); 585 586 /* Ensure that the bit position is a valid one */ 587 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 588 589 /* Ensure that the 'value' is only a bit wide */ 590 assert(value <= 1U); 591 592 /* 593 * Get the SCR_EL3 value from the cpu context, clear the desired bit 594 * and set it to its new value. 595 */ 596 state = get_el3state_ctx(ctx); 597 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 598 scr_el3 &= ~(1U << bit_pos); 599 scr_el3 |= value << bit_pos; 600 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 601 } 602 603 /******************************************************************************* 604 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 605 * given security state. 606 ******************************************************************************/ 607 uint32_t cm_get_scr_el3(uint32_t security_state) 608 { 609 cpu_context_t *ctx; 610 el3_state_t *state; 611 612 ctx = cm_get_context(security_state); 613 assert(ctx != NULL); 614 615 /* Populate EL3 state so that ERET jumps to the correct entry */ 616 state = get_el3state_ctx(ctx); 617 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 618 } 619 620 /******************************************************************************* 621 * This function is used to program the context that's used for exception 622 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 623 * the required security state 624 ******************************************************************************/ 625 void cm_set_next_eret_context(uint32_t security_state) 626 { 627 cpu_context_t *ctx; 628 629 ctx = cm_get_context(security_state); 630 assert(ctx != NULL); 631 632 cm_set_next_context(ctx); 633 } 634