1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/utils.h> 26 #include <plat/common/platform.h> 27 #include <smccc_helpers.h> 28 29 30 /******************************************************************************* 31 * Context management library initialisation routine. This library is used by 32 * runtime services to share pointers to 'cpu_context' structures for the secure 33 * and non-secure states. Management of the structures and their associated 34 * memory is not done by the context management library e.g. the PSCI service 35 * manages the cpu context used for entry from and exit to the non-secure state. 36 * The Secure payload dispatcher service manages the context(s) corresponding to 37 * the secure state. It also uses this library to get access to the non-secure 38 * state cpu context pointers. 39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 40 * which will used for programming an entry into a lower EL. The same context 41 * will used to save state upon exception entry from that EL. 42 ******************************************************************************/ 43 void __init cm_init(void) 44 { 45 /* 46 * The context management library has only global data to intialize, but 47 * that will be done when the BSS is zeroed out 48 */ 49 } 50 51 /******************************************************************************* 52 * The following function initializes the cpu_context 'ctx' for 53 * first use, and sets the initial entrypoint state as specified by the 54 * entry_point_info structure. 55 * 56 * The security state to initialize is determined by the SECURE attribute 57 * of the entry_point_info. 58 * 59 * The EE and ST attributes are used to configure the endianness and secure 60 * timer availability for the new execution context. 61 * 62 * To prepare the register state for entry call cm_prepare_el3_exit() and 63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 64 * cm_e1_sysreg_context_restore(). 65 ******************************************************************************/ 66 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 67 { 68 unsigned int security_state; 69 uint32_t scr_el3; 70 el3_state_t *state; 71 gp_regs_t *gp_regs; 72 u_register_t sctlr_elx, actlr_elx; 73 74 assert(ctx != NULL); 75 76 security_state = GET_SECURITY_STATE(ep->h.attr); 77 78 /* Clear any residual register values from the context */ 79 zeromem(ctx, sizeof(*ctx)); 80 81 /* 82 * SCR_EL3 was initialised during reset sequence in macro 83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 84 * affect the next EL. 85 * 86 * The following fields are initially set to zero and then updated to 87 * the required value depending on the state of the SPSR_EL3 and the 88 * Security state and entrypoint attributes of the next EL. 89 */ 90 scr_el3 = (uint32_t)read_scr(); 91 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 92 SCR_ST_BIT | SCR_HCE_BIT); 93 /* 94 * SCR_NS: Set the security state of the next EL. 95 */ 96 if (security_state != SECURE) 97 scr_el3 |= SCR_NS_BIT; 98 /* 99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 100 * Exception level as specified by SPSR. 101 */ 102 if (GET_RW(ep->spsr) == MODE_RW_64) 103 scr_el3 |= SCR_RW_BIT; 104 /* 105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 106 * Secure timer registers to EL3, from AArch64 state only, if specified 107 * by the entrypoint attributes. 108 */ 109 if (EP_GET_ST(ep->h.attr) != 0U) 110 scr_el3 |= SCR_ST_BIT; 111 112 #if !HANDLE_EA_EL3_FIRST 113 /* 114 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 115 * to EL3 when executing at a lower EL. When executing at EL3, External 116 * Aborts are taken to EL3. 117 */ 118 scr_el3 &= ~SCR_EA_BIT; 119 #endif 120 121 #if FAULT_INJECTION_SUPPORT 122 /* Enable fault injection from lower ELs */ 123 scr_el3 |= SCR_FIEN_BIT; 124 #endif 125 126 #if !CTX_INCLUDE_PAUTH_REGS 127 /* 128 * If the pointer authentication registers aren't saved during world 129 * switches the value of the registers can be leaked from the Secure to 130 * the Non-secure world. To prevent this, rather than enabling pointer 131 * authentication everywhere, we only enable it in the Non-secure world. 132 * 133 * If the Secure world wants to use pointer authentication, 134 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 135 */ 136 if (security_state == NON_SECURE) 137 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 138 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 139 140 /* 141 * Enable MTE support. Support is enabled unilaterally for the normal 142 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 143 * set. 144 */ 145 #if CTX_INCLUDE_MTE_REGS 146 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 147 scr_el3 |= SCR_ATA_BIT; 148 #else 149 unsigned int mte = get_armv8_5_mte_support(); 150 if (mte == MTE_IMPLEMENTED_EL0) { 151 /* 152 * Can enable MTE across both worlds as no MTE registers are 153 * used 154 */ 155 scr_el3 |= SCR_ATA_BIT; 156 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 157 /* 158 * Can only enable MTE in Non-Secure world without register 159 * saving 160 */ 161 scr_el3 |= SCR_ATA_BIT; 162 } 163 #endif 164 165 #ifdef IMAGE_BL31 166 /* 167 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 168 * indicated by the interrupt routing model for BL31. 169 */ 170 scr_el3 |= get_scr_el3_from_routing_model(security_state); 171 #endif 172 173 /* 174 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 175 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 176 * next mode is Hyp. 177 */ 178 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 179 || ((GET_RW(ep->spsr) != MODE_RW_64) 180 && (GET_M32(ep->spsr) == MODE32_hyp))) { 181 scr_el3 |= SCR_HCE_BIT; 182 } 183 184 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 185 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 186 if (GET_RW(ep->spsr) != MODE_RW_64) { 187 ERROR("S-EL2 can not be used in AArch32."); 188 panic(); 189 } 190 191 scr_el3 |= SCR_EEL2_BIT; 192 } 193 194 /* 195 * Initialise SCTLR_EL1 to the reset value corresponding to the target 196 * execution state setting all fields rather than relying of the hw. 197 * Some fields have architecturally UNKNOWN reset values and these are 198 * set to zero. 199 * 200 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 201 * 202 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 203 * required by PSCI specification) 204 */ 205 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 206 if (GET_RW(ep->spsr) == MODE_RW_64) 207 sctlr_elx |= SCTLR_EL1_RES1; 208 else { 209 /* 210 * If the target execution state is AArch32 then the following 211 * fields need to be set. 212 * 213 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 214 * instructions are not trapped to EL1. 215 * 216 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 217 * instructions are not trapped to EL1. 218 * 219 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 220 * CP15DMB, CP15DSB, and CP15ISB instructions. 221 */ 222 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 223 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 224 } 225 226 #if ERRATA_A75_764081 227 /* 228 * If workaround of errata 764081 for Cortex-A75 is used then set 229 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 230 */ 231 sctlr_elx |= SCTLR_IESB_BIT; 232 #endif 233 234 /* 235 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 236 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 237 * are not part of the stored cpu_context. 238 */ 239 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 240 241 /* 242 * Base the context ACTLR_EL1 on the current value, as it is 243 * implementation defined. The context restore process will write 244 * the value from the context to the actual register and can cause 245 * problems for processor cores that don't expect certain bits to 246 * be zero. 247 */ 248 actlr_elx = read_actlr_el1(); 249 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 250 251 /* 252 * Populate EL3 state so that we've the right context 253 * before doing ERET 254 */ 255 state = get_el3state_ctx(ctx); 256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 257 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 258 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 259 260 /* 261 * Store the X0-X7 value from the entrypoint into the context 262 * Use memcpy as we are in control of the layout of the structures 263 */ 264 gp_regs = get_gpregs_ctx(ctx); 265 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 266 } 267 268 /******************************************************************************* 269 * Enable architecture extensions on first entry to Non-secure world. 270 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 271 * it is zero. 272 ******************************************************************************/ 273 static void enable_extensions_nonsecure(bool el2_unused) 274 { 275 #if IMAGE_BL31 276 #if ENABLE_SPE_FOR_LOWER_ELS 277 spe_enable(el2_unused); 278 #endif 279 280 #if ENABLE_AMU 281 amu_enable(el2_unused); 282 #endif 283 284 #if ENABLE_SVE_FOR_NS 285 sve_enable(el2_unused); 286 #endif 287 288 #if ENABLE_MPAM_FOR_LOWER_ELS 289 mpam_enable(el2_unused); 290 #endif 291 #endif 292 } 293 294 /******************************************************************************* 295 * The following function initializes the cpu_context for a CPU specified by 296 * its `cpu_idx` for first use, and sets the initial entrypoint state as 297 * specified by the entry_point_info structure. 298 ******************************************************************************/ 299 void cm_init_context_by_index(unsigned int cpu_idx, 300 const entry_point_info_t *ep) 301 { 302 cpu_context_t *ctx; 303 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 304 cm_setup_context(ctx, ep); 305 } 306 307 /******************************************************************************* 308 * The following function initializes the cpu_context for the current CPU 309 * for first use, and sets the initial entrypoint state as specified by the 310 * entry_point_info structure. 311 ******************************************************************************/ 312 void cm_init_my_context(const entry_point_info_t *ep) 313 { 314 cpu_context_t *ctx; 315 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 316 cm_setup_context(ctx, ep); 317 } 318 319 /******************************************************************************* 320 * Prepare the CPU system registers for first entry into secure or normal world 321 * 322 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 323 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 324 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 325 * For all entries, the EL1 registers are initialized from the cpu_context 326 ******************************************************************************/ 327 void cm_prepare_el3_exit(uint32_t security_state) 328 { 329 uint32_t sctlr_elx, scr_el3, mdcr_el2; 330 cpu_context_t *ctx = cm_get_context(security_state); 331 bool el2_unused = false; 332 uint64_t hcr_el2 = 0U; 333 334 assert(ctx != NULL); 335 336 if (security_state == NON_SECURE) { 337 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 338 CTX_SCR_EL3); 339 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 340 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 341 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 342 CTX_SCTLR_EL1); 343 sctlr_elx &= SCTLR_EE_BIT; 344 sctlr_elx |= SCTLR_EL2_RES1; 345 #if ERRATA_A75_764081 346 /* 347 * If workaround of errata 764081 for Cortex-A75 is used 348 * then set SCTLR_EL2.IESB to enable Implicit Error 349 * Synchronization Barrier. 350 */ 351 sctlr_elx |= SCTLR_IESB_BIT; 352 #endif 353 write_sctlr_el2(sctlr_elx); 354 } else if (el_implemented(2) != EL_IMPL_NONE) { 355 el2_unused = true; 356 357 /* 358 * EL2 present but unused, need to disable safely. 359 * SCTLR_EL2 can be ignored in this case. 360 * 361 * Set EL2 register width appropriately: Set HCR_EL2 362 * field to match SCR_EL3.RW. 363 */ 364 if ((scr_el3 & SCR_RW_BIT) != 0U) 365 hcr_el2 |= HCR_RW_BIT; 366 367 /* 368 * For Armv8.3 pointer authentication feature, disable 369 * traps to EL2 when accessing key registers or using 370 * pointer authentication instructions from lower ELs. 371 */ 372 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 373 374 write_hcr_el2(hcr_el2); 375 376 /* 377 * Initialise CPTR_EL2 setting all fields rather than 378 * relying on the hw. All fields have architecturally 379 * UNKNOWN reset values. 380 * 381 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 382 * accesses to the CPACR_EL1 or CPACR from both 383 * Execution states do not trap to EL2. 384 * 385 * CPTR_EL2.TTA: Set to zero so that Non-secure System 386 * register accesses to the trace registers from both 387 * Execution states do not trap to EL2. 388 * 389 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 390 * to SIMD and floating-point functionality from both 391 * Execution states do not trap to EL2. 392 */ 393 write_cptr_el2(CPTR_EL2_RESET_VAL & 394 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 395 | CPTR_EL2_TFP_BIT)); 396 397 /* 398 * Initialise CNTHCTL_EL2. All fields are 399 * architecturally UNKNOWN on reset and are set to zero 400 * except for field(s) listed below. 401 * 402 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 403 * Hyp mode of Non-secure EL0 and EL1 accesses to the 404 * physical timer registers. 405 * 406 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 407 * Hyp mode of Non-secure EL0 and EL1 accesses to the 408 * physical counter registers. 409 */ 410 write_cnthctl_el2(CNTHCTL_RESET_VAL | 411 EL1PCEN_BIT | EL1PCTEN_BIT); 412 413 /* 414 * Initialise CNTVOFF_EL2 to zero as it resets to an 415 * architecturally UNKNOWN value. 416 */ 417 write_cntvoff_el2(0); 418 419 /* 420 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 421 * MPIDR_EL1 respectively. 422 */ 423 write_vpidr_el2(read_midr_el1()); 424 write_vmpidr_el2(read_mpidr_el1()); 425 426 /* 427 * Initialise VTTBR_EL2. All fields are architecturally 428 * UNKNOWN on reset. 429 * 430 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 431 * 2 address translation is disabled, cache maintenance 432 * operations depend on the VMID. 433 * 434 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 435 * translation is disabled. 436 */ 437 write_vttbr_el2(VTTBR_RESET_VAL & 438 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 439 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 440 441 /* 442 * Initialise MDCR_EL2, setting all fields rather than 443 * relying on hw. Some fields are architecturally 444 * UNKNOWN on reset. 445 * 446 * MDCR_EL2.HLP: Set to one so that event counter 447 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 448 * occurs on the increment that changes 449 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 450 * implemented. This bit is RES0 in versions of the 451 * architecture earlier than ARMv8.5, setting it to 1 452 * doesn't have any effect on them. 453 * 454 * MDCR_EL2.TTRF: Set to zero so that access to Trace 455 * Filter Control register TRFCR_EL1 at EL1 is not 456 * trapped to EL2. This bit is RES0 in versions of 457 * the architecture earlier than ARMv8.4. 458 * 459 * MDCR_EL2.HPMD: Set to one so that event counting is 460 * prohibited at EL2. This bit is RES0 in versions of 461 * the architecture earlier than ARMv8.1, setting it 462 * to 1 doesn't have any effect on them. 463 * 464 * MDCR_EL2.TPMS: Set to zero so that accesses to 465 * Statistical Profiling control registers from EL1 466 * do not trap to EL2. This bit is RES0 when SPE is 467 * not implemented. 468 * 469 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 470 * EL1 System register accesses to the Debug ROM 471 * registers are not trapped to EL2. 472 * 473 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 474 * System register accesses to the powerdown debug 475 * registers are not trapped to EL2. 476 * 477 * MDCR_EL2.TDA: Set to zero so that System register 478 * accesses to the debug registers do not trap to EL2. 479 * 480 * MDCR_EL2.TDE: Set to zero so that debug exceptions 481 * are not routed to EL2. 482 * 483 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 484 * Monitors. 485 * 486 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 487 * EL1 accesses to all Performance Monitors registers 488 * are not trapped to EL2. 489 * 490 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 491 * and EL1 accesses to the PMCR_EL0 or PMCR are not 492 * trapped to EL2. 493 * 494 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 495 * architecturally-defined reset value. 496 */ 497 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 498 MDCR_EL2_HPMD) | 499 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 500 >> PMCR_EL0_N_SHIFT)) & 501 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 502 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 503 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 504 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 505 MDCR_EL2_TPMCR_BIT); 506 507 write_mdcr_el2(mdcr_el2); 508 509 /* 510 * Initialise HSTR_EL2. All fields are architecturally 511 * UNKNOWN on reset. 512 * 513 * HSTR_EL2.T<n>: Set all these fields to zero so that 514 * Non-secure EL0 or EL1 accesses to System registers 515 * do not trap to EL2. 516 */ 517 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 518 /* 519 * Initialise CNTHP_CTL_EL2. All fields are 520 * architecturally UNKNOWN on reset. 521 * 522 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 523 * physical timer and prevent timer interrupts. 524 */ 525 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 526 ~(CNTHP_CTL_ENABLE_BIT)); 527 } 528 enable_extensions_nonsecure(el2_unused); 529 } 530 531 cm_el1_sysregs_context_restore(security_state); 532 cm_set_next_eret_context(security_state); 533 } 534 535 /******************************************************************************* 536 * The next four functions are used by runtime services to save and restore 537 * EL1 context on the 'cpu_context' structure for the specified security 538 * state. 539 ******************************************************************************/ 540 void cm_el1_sysregs_context_save(uint32_t security_state) 541 { 542 cpu_context_t *ctx; 543 544 ctx = cm_get_context(security_state); 545 assert(ctx != NULL); 546 547 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 548 549 #if IMAGE_BL31 550 if (security_state == SECURE) 551 PUBLISH_EVENT(cm_exited_secure_world); 552 else 553 PUBLISH_EVENT(cm_exited_normal_world); 554 #endif 555 } 556 557 void cm_el1_sysregs_context_restore(uint32_t security_state) 558 { 559 cpu_context_t *ctx; 560 561 ctx = cm_get_context(security_state); 562 assert(ctx != NULL); 563 564 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 565 566 #if IMAGE_BL31 567 if (security_state == SECURE) 568 PUBLISH_EVENT(cm_entering_secure_world); 569 else 570 PUBLISH_EVENT(cm_entering_normal_world); 571 #endif 572 } 573 574 /******************************************************************************* 575 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 576 * given security state with the given entrypoint 577 ******************************************************************************/ 578 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 579 { 580 cpu_context_t *ctx; 581 el3_state_t *state; 582 583 ctx = cm_get_context(security_state); 584 assert(ctx != NULL); 585 586 /* Populate EL3 state so that ERET jumps to the correct entry */ 587 state = get_el3state_ctx(ctx); 588 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 589 } 590 591 /******************************************************************************* 592 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 593 * pertaining to the given security state 594 ******************************************************************************/ 595 void cm_set_elr_spsr_el3(uint32_t security_state, 596 uintptr_t entrypoint, uint32_t spsr) 597 { 598 cpu_context_t *ctx; 599 el3_state_t *state; 600 601 ctx = cm_get_context(security_state); 602 assert(ctx != NULL); 603 604 /* Populate EL3 state so that ERET jumps to the correct entry */ 605 state = get_el3state_ctx(ctx); 606 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 607 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 608 } 609 610 /******************************************************************************* 611 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 612 * pertaining to the given security state using the value and bit position 613 * specified in the parameters. It preserves all other bits. 614 ******************************************************************************/ 615 void cm_write_scr_el3_bit(uint32_t security_state, 616 uint32_t bit_pos, 617 uint32_t value) 618 { 619 cpu_context_t *ctx; 620 el3_state_t *state; 621 uint32_t scr_el3; 622 623 ctx = cm_get_context(security_state); 624 assert(ctx != NULL); 625 626 /* Ensure that the bit position is a valid one */ 627 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 628 629 /* Ensure that the 'value' is only a bit wide */ 630 assert(value <= 1U); 631 632 /* 633 * Get the SCR_EL3 value from the cpu context, clear the desired bit 634 * and set it to its new value. 635 */ 636 state = get_el3state_ctx(ctx); 637 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 638 scr_el3 &= ~(1U << bit_pos); 639 scr_el3 |= value << bit_pos; 640 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 641 } 642 643 /******************************************************************************* 644 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 645 * given security state. 646 ******************************************************************************/ 647 uint32_t cm_get_scr_el3(uint32_t security_state) 648 { 649 cpu_context_t *ctx; 650 el3_state_t *state; 651 652 ctx = cm_get_context(security_state); 653 assert(ctx != NULL); 654 655 /* Populate EL3 state so that ERET jumps to the correct entry */ 656 state = get_el3state_ctx(ctx); 657 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 658 } 659 660 /******************************************************************************* 661 * This function is used to program the context that's used for exception 662 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 663 * the required security state 664 ******************************************************************************/ 665 void cm_set_next_eret_context(uint32_t security_state) 666 { 667 cpu_context_t *ctx; 668 669 ctx = cm_get_context(security_state); 670 assert(ctx != NULL); 671 672 cm_set_next_context(ctx); 673 } 674