1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/utils.h> 26 #include <plat/common/platform.h> 27 #include <smccc_helpers.h> 28 29 30 /******************************************************************************* 31 * Context management library initialisation routine. This library is used by 32 * runtime services to share pointers to 'cpu_context' structures for the secure 33 * and non-secure states. Management of the structures and their associated 34 * memory is not done by the context management library e.g. the PSCI service 35 * manages the cpu context used for entry from and exit to the non-secure state. 36 * The Secure payload dispatcher service manages the context(s) corresponding to 37 * the secure state. It also uses this library to get access to the non-secure 38 * state cpu context pointers. 39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 40 * which will used for programming an entry into a lower EL. The same context 41 * will used to save state upon exception entry from that EL. 42 ******************************************************************************/ 43 void __init cm_init(void) 44 { 45 /* 46 * The context management library has only global data to intialize, but 47 * that will be done when the BSS is zeroed out 48 */ 49 } 50 51 /******************************************************************************* 52 * The following function initializes the cpu_context 'ctx' for 53 * first use, and sets the initial entrypoint state as specified by the 54 * entry_point_info structure. 55 * 56 * The security state to initialize is determined by the SECURE attribute 57 * of the entry_point_info. 58 * 59 * The EE and ST attributes are used to configure the endianness and secure 60 * timer availability for the new execution context. 61 * 62 * To prepare the register state for entry call cm_prepare_el3_exit() and 63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 64 * cm_e1_sysreg_context_restore(). 65 ******************************************************************************/ 66 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 67 { 68 unsigned int security_state; 69 uint32_t scr_el3; 70 el3_state_t *state; 71 gp_regs_t *gp_regs; 72 u_register_t sctlr_elx, actlr_elx; 73 74 assert(ctx != NULL); 75 76 security_state = GET_SECURITY_STATE(ep->h.attr); 77 78 /* Clear any residual register values from the context */ 79 zeromem(ctx, sizeof(*ctx)); 80 81 /* 82 * SCR_EL3 was initialised during reset sequence in macro 83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 84 * affect the next EL. 85 * 86 * The following fields are initially set to zero and then updated to 87 * the required value depending on the state of the SPSR_EL3 and the 88 * Security state and entrypoint attributes of the next EL. 89 */ 90 scr_el3 = (uint32_t)read_scr(); 91 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 92 SCR_ST_BIT | SCR_HCE_BIT); 93 /* 94 * SCR_NS: Set the security state of the next EL. 95 */ 96 if (security_state != SECURE) 97 scr_el3 |= SCR_NS_BIT; 98 /* 99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 100 * Exception level as specified by SPSR. 101 */ 102 if (GET_RW(ep->spsr) == MODE_RW_64) 103 scr_el3 |= SCR_RW_BIT; 104 /* 105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 106 * Secure timer registers to EL3, from AArch64 state only, if specified 107 * by the entrypoint attributes. 108 */ 109 if (EP_GET_ST(ep->h.attr) != 0U) 110 scr_el3 |= SCR_ST_BIT; 111 112 #if !HANDLE_EA_EL3_FIRST 113 /* 114 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 115 * to EL3 when executing at a lower EL. When executing at EL3, External 116 * Aborts are taken to EL3. 117 */ 118 scr_el3 &= ~SCR_EA_BIT; 119 #endif 120 121 #if FAULT_INJECTION_SUPPORT 122 /* Enable fault injection from lower ELs */ 123 scr_el3 |= SCR_FIEN_BIT; 124 #endif 125 126 #if !CTX_INCLUDE_PAUTH_REGS 127 /* 128 * If the pointer authentication registers aren't saved during world 129 * switches the value of the registers can be leaked from the Secure to 130 * the Non-secure world. To prevent this, rather than enabling pointer 131 * authentication everywhere, we only enable it in the Non-secure world. 132 * 133 * If the Secure world wants to use pointer authentication, 134 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 135 */ 136 if (security_state == NON_SECURE) 137 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 138 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 139 140 /* 141 * Enable MTE support. Support is enabled unilaterally for the normal 142 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 143 * set. 144 */ 145 #if CTX_INCLUDE_MTE_REGS 146 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 147 scr_el3 |= SCR_ATA_BIT; 148 #else 149 unsigned int mte = get_armv8_5_mte_support(); 150 if (mte == MTE_IMPLEMENTED_EL0) { 151 /* 152 * Can enable MTE across both worlds as no MTE registers are 153 * used 154 */ 155 scr_el3 |= SCR_ATA_BIT; 156 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 157 /* 158 * Can only enable MTE in Non-Secure world without register 159 * saving 160 */ 161 scr_el3 |= SCR_ATA_BIT; 162 } 163 #endif 164 165 #ifdef IMAGE_BL31 166 /* 167 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 168 * indicated by the interrupt routing model for BL31. 169 */ 170 scr_el3 |= get_scr_el3_from_routing_model(security_state); 171 #endif 172 173 /* 174 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 175 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 176 * next mode is Hyp. 177 */ 178 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 179 || ((GET_RW(ep->spsr) != MODE_RW_64) 180 && (GET_M32(ep->spsr) == MODE32_hyp))) { 181 scr_el3 |= SCR_HCE_BIT; 182 } 183 184 /* 185 * Initialise SCTLR_EL1 to the reset value corresponding to the target 186 * execution state setting all fields rather than relying of the hw. 187 * Some fields have architecturally UNKNOWN reset values and these are 188 * set to zero. 189 * 190 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 191 * 192 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 193 * required by PSCI specification) 194 */ 195 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 196 if (GET_RW(ep->spsr) == MODE_RW_64) 197 sctlr_elx |= SCTLR_EL1_RES1; 198 else { 199 /* 200 * If the target execution state is AArch32 then the following 201 * fields need to be set. 202 * 203 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 204 * instructions are not trapped to EL1. 205 * 206 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 207 * instructions are not trapped to EL1. 208 * 209 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 210 * CP15DMB, CP15DSB, and CP15ISB instructions. 211 */ 212 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 213 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 214 } 215 216 #if ERRATA_A75_764081 217 /* 218 * If workaround of errata 764081 for Cortex-A75 is used then set 219 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 220 */ 221 sctlr_elx |= SCTLR_IESB_BIT; 222 #endif 223 224 /* 225 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 226 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 227 * are not part of the stored cpu_context. 228 */ 229 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 230 231 /* 232 * Base the context ACTLR_EL1 on the current value, as it is 233 * implementation defined. The context restore process will write 234 * the value from the context to the actual register and can cause 235 * problems for processor cores that don't expect certain bits to 236 * be zero. 237 */ 238 actlr_elx = read_actlr_el1(); 239 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 240 241 /* 242 * Populate EL3 state so that we've the right context 243 * before doing ERET 244 */ 245 state = get_el3state_ctx(ctx); 246 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 247 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 248 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 249 250 /* 251 * Store the X0-X7 value from the entrypoint into the context 252 * Use memcpy as we are in control of the layout of the structures 253 */ 254 gp_regs = get_gpregs_ctx(ctx); 255 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 256 } 257 258 /******************************************************************************* 259 * Enable architecture extensions on first entry to Non-secure world. 260 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 261 * it is zero. 262 ******************************************************************************/ 263 static void enable_extensions_nonsecure(bool el2_unused) 264 { 265 #if IMAGE_BL31 266 #if ENABLE_SPE_FOR_LOWER_ELS 267 spe_enable(el2_unused); 268 #endif 269 270 #if ENABLE_AMU 271 amu_enable(el2_unused); 272 #endif 273 274 #if ENABLE_SVE_FOR_NS 275 sve_enable(el2_unused); 276 #endif 277 278 #if ENABLE_MPAM_FOR_LOWER_ELS 279 mpam_enable(el2_unused); 280 #endif 281 #endif 282 } 283 284 /******************************************************************************* 285 * The following function initializes the cpu_context for a CPU specified by 286 * its `cpu_idx` for first use, and sets the initial entrypoint state as 287 * specified by the entry_point_info structure. 288 ******************************************************************************/ 289 void cm_init_context_by_index(unsigned int cpu_idx, 290 const entry_point_info_t *ep) 291 { 292 cpu_context_t *ctx; 293 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 294 cm_setup_context(ctx, ep); 295 } 296 297 /******************************************************************************* 298 * The following function initializes the cpu_context for the current CPU 299 * for first use, and sets the initial entrypoint state as specified by the 300 * entry_point_info structure. 301 ******************************************************************************/ 302 void cm_init_my_context(const entry_point_info_t *ep) 303 { 304 cpu_context_t *ctx; 305 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 306 cm_setup_context(ctx, ep); 307 } 308 309 /******************************************************************************* 310 * Prepare the CPU system registers for first entry into secure or normal world 311 * 312 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 313 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 314 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 315 * For all entries, the EL1 registers are initialized from the cpu_context 316 ******************************************************************************/ 317 void cm_prepare_el3_exit(uint32_t security_state) 318 { 319 uint32_t sctlr_elx, scr_el3, mdcr_el2; 320 cpu_context_t *ctx = cm_get_context(security_state); 321 bool el2_unused = false; 322 uint64_t hcr_el2 = 0U; 323 324 assert(ctx != NULL); 325 326 if (security_state == NON_SECURE) { 327 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 328 CTX_SCR_EL3); 329 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 330 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 331 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 332 CTX_SCTLR_EL1); 333 sctlr_elx &= SCTLR_EE_BIT; 334 sctlr_elx |= SCTLR_EL2_RES1; 335 #if ERRATA_A75_764081 336 /* 337 * If workaround of errata 764081 for Cortex-A75 is used 338 * then set SCTLR_EL2.IESB to enable Implicit Error 339 * Synchronization Barrier. 340 */ 341 sctlr_elx |= SCTLR_IESB_BIT; 342 #endif 343 write_sctlr_el2(sctlr_elx); 344 } else if (el_implemented(2) != EL_IMPL_NONE) { 345 el2_unused = true; 346 347 /* 348 * EL2 present but unused, need to disable safely. 349 * SCTLR_EL2 can be ignored in this case. 350 * 351 * Set EL2 register width appropriately: Set HCR_EL2 352 * field to match SCR_EL3.RW. 353 */ 354 if ((scr_el3 & SCR_RW_BIT) != 0U) 355 hcr_el2 |= HCR_RW_BIT; 356 357 /* 358 * For Armv8.3 pointer authentication feature, disable 359 * traps to EL2 when accessing key registers or using 360 * pointer authentication instructions from lower ELs. 361 */ 362 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 363 364 write_hcr_el2(hcr_el2); 365 366 /* 367 * Initialise CPTR_EL2 setting all fields rather than 368 * relying on the hw. All fields have architecturally 369 * UNKNOWN reset values. 370 * 371 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 372 * accesses to the CPACR_EL1 or CPACR from both 373 * Execution states do not trap to EL2. 374 * 375 * CPTR_EL2.TTA: Set to zero so that Non-secure System 376 * register accesses to the trace registers from both 377 * Execution states do not trap to EL2. 378 * 379 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 380 * to SIMD and floating-point functionality from both 381 * Execution states do not trap to EL2. 382 */ 383 write_cptr_el2(CPTR_EL2_RESET_VAL & 384 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 385 | CPTR_EL2_TFP_BIT)); 386 387 /* 388 * Initialise CNTHCTL_EL2. All fields are 389 * architecturally UNKNOWN on reset and are set to zero 390 * except for field(s) listed below. 391 * 392 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 393 * Hyp mode of Non-secure EL0 and EL1 accesses to the 394 * physical timer registers. 395 * 396 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 397 * Hyp mode of Non-secure EL0 and EL1 accesses to the 398 * physical counter registers. 399 */ 400 write_cnthctl_el2(CNTHCTL_RESET_VAL | 401 EL1PCEN_BIT | EL1PCTEN_BIT); 402 403 /* 404 * Initialise CNTVOFF_EL2 to zero as it resets to an 405 * architecturally UNKNOWN value. 406 */ 407 write_cntvoff_el2(0); 408 409 /* 410 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 411 * MPIDR_EL1 respectively. 412 */ 413 write_vpidr_el2(read_midr_el1()); 414 write_vmpidr_el2(read_mpidr_el1()); 415 416 /* 417 * Initialise VTTBR_EL2. All fields are architecturally 418 * UNKNOWN on reset. 419 * 420 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 421 * 2 address translation is disabled, cache maintenance 422 * operations depend on the VMID. 423 * 424 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 425 * translation is disabled. 426 */ 427 write_vttbr_el2(VTTBR_RESET_VAL & 428 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 429 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 430 431 /* 432 * Initialise MDCR_EL2, setting all fields rather than 433 * relying on hw. Some fields are architecturally 434 * UNKNOWN on reset. 435 * 436 * MDCR_EL2.HLP: Set to one so that event counter 437 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 438 * occurs on the increment that changes 439 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 440 * implemented. This bit is RES0 in versions of the 441 * architecture earlier than ARMv8.5, setting it to 1 442 * doesn't have any effect on them. 443 * 444 * MDCR_EL2.TTRF: Set to zero so that access to Trace 445 * Filter Control register TRFCR_EL1 at EL1 is not 446 * trapped to EL2. This bit is RES0 in versions of 447 * the architecture earlier than ARMv8.4. 448 * 449 * MDCR_EL2.HPMD: Set to one so that event counting is 450 * prohibited at EL2. This bit is RES0 in versions of 451 * the architecture earlier than ARMv8.1, setting it 452 * to 1 doesn't have any effect on them. 453 * 454 * MDCR_EL2.TPMS: Set to zero so that accesses to 455 * Statistical Profiling control registers from EL1 456 * do not trap to EL2. This bit is RES0 when SPE is 457 * not implemented. 458 * 459 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 460 * EL1 System register accesses to the Debug ROM 461 * registers are not trapped to EL2. 462 * 463 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 464 * System register accesses to the powerdown debug 465 * registers are not trapped to EL2. 466 * 467 * MDCR_EL2.TDA: Set to zero so that System register 468 * accesses to the debug registers do not trap to EL2. 469 * 470 * MDCR_EL2.TDE: Set to zero so that debug exceptions 471 * are not routed to EL2. 472 * 473 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 474 * Monitors. 475 * 476 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 477 * EL1 accesses to all Performance Monitors registers 478 * are not trapped to EL2. 479 * 480 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 481 * and EL1 accesses to the PMCR_EL0 or PMCR are not 482 * trapped to EL2. 483 * 484 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 485 * architecturally-defined reset value. 486 */ 487 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 488 MDCR_EL2_HPMD) | 489 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 490 >> PMCR_EL0_N_SHIFT)) & 491 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 492 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 493 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 494 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 495 MDCR_EL2_TPMCR_BIT); 496 497 write_mdcr_el2(mdcr_el2); 498 499 /* 500 * Initialise HSTR_EL2. All fields are architecturally 501 * UNKNOWN on reset. 502 * 503 * HSTR_EL2.T<n>: Set all these fields to zero so that 504 * Non-secure EL0 or EL1 accesses to System registers 505 * do not trap to EL2. 506 */ 507 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 508 /* 509 * Initialise CNTHP_CTL_EL2. All fields are 510 * architecturally UNKNOWN on reset. 511 * 512 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 513 * physical timer and prevent timer interrupts. 514 */ 515 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 516 ~(CNTHP_CTL_ENABLE_BIT)); 517 } 518 enable_extensions_nonsecure(el2_unused); 519 } 520 521 cm_el1_sysregs_context_restore(security_state); 522 cm_set_next_eret_context(security_state); 523 } 524 525 /******************************************************************************* 526 * The next four functions are used by runtime services to save and restore 527 * EL1 context on the 'cpu_context' structure for the specified security 528 * state. 529 ******************************************************************************/ 530 void cm_el1_sysregs_context_save(uint32_t security_state) 531 { 532 cpu_context_t *ctx; 533 534 ctx = cm_get_context(security_state); 535 assert(ctx != NULL); 536 537 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 538 539 #if IMAGE_BL31 540 if (security_state == SECURE) 541 PUBLISH_EVENT(cm_exited_secure_world); 542 else 543 PUBLISH_EVENT(cm_exited_normal_world); 544 #endif 545 } 546 547 void cm_el1_sysregs_context_restore(uint32_t security_state) 548 { 549 cpu_context_t *ctx; 550 551 ctx = cm_get_context(security_state); 552 assert(ctx != NULL); 553 554 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 555 556 #if IMAGE_BL31 557 if (security_state == SECURE) 558 PUBLISH_EVENT(cm_entering_secure_world); 559 else 560 PUBLISH_EVENT(cm_entering_normal_world); 561 #endif 562 } 563 564 /******************************************************************************* 565 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 566 * given security state with the given entrypoint 567 ******************************************************************************/ 568 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 569 { 570 cpu_context_t *ctx; 571 el3_state_t *state; 572 573 ctx = cm_get_context(security_state); 574 assert(ctx != NULL); 575 576 /* Populate EL3 state so that ERET jumps to the correct entry */ 577 state = get_el3state_ctx(ctx); 578 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 579 } 580 581 /******************************************************************************* 582 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 583 * pertaining to the given security state 584 ******************************************************************************/ 585 void cm_set_elr_spsr_el3(uint32_t security_state, 586 uintptr_t entrypoint, uint32_t spsr) 587 { 588 cpu_context_t *ctx; 589 el3_state_t *state; 590 591 ctx = cm_get_context(security_state); 592 assert(ctx != NULL); 593 594 /* Populate EL3 state so that ERET jumps to the correct entry */ 595 state = get_el3state_ctx(ctx); 596 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 597 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 598 } 599 600 /******************************************************************************* 601 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 602 * pertaining to the given security state using the value and bit position 603 * specified in the parameters. It preserves all other bits. 604 ******************************************************************************/ 605 void cm_write_scr_el3_bit(uint32_t security_state, 606 uint32_t bit_pos, 607 uint32_t value) 608 { 609 cpu_context_t *ctx; 610 el3_state_t *state; 611 uint32_t scr_el3; 612 613 ctx = cm_get_context(security_state); 614 assert(ctx != NULL); 615 616 /* Ensure that the bit position is a valid one */ 617 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 618 619 /* Ensure that the 'value' is only a bit wide */ 620 assert(value <= 1U); 621 622 /* 623 * Get the SCR_EL3 value from the cpu context, clear the desired bit 624 * and set it to its new value. 625 */ 626 state = get_el3state_ctx(ctx); 627 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 628 scr_el3 &= ~(1U << bit_pos); 629 scr_el3 |= value << bit_pos; 630 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 631 } 632 633 /******************************************************************************* 634 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 635 * given security state. 636 ******************************************************************************/ 637 uint32_t cm_get_scr_el3(uint32_t security_state) 638 { 639 cpu_context_t *ctx; 640 el3_state_t *state; 641 642 ctx = cm_get_context(security_state); 643 assert(ctx != NULL); 644 645 /* Populate EL3 state so that ERET jumps to the correct entry */ 646 state = get_el3state_ctx(ctx); 647 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 648 } 649 650 /******************************************************************************* 651 * This function is used to program the context that's used for exception 652 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 653 * the required security state 654 ******************************************************************************/ 655 void cm_set_next_eret_context(uint32_t security_state) 656 { 657 cpu_context_t *ctx; 658 659 ctx = cm_get_context(security_state); 660 assert(ctx != NULL); 661 662 cm_set_next_context(ctx); 663 } 664