1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 } 195 #endif /* ENABLE_RME */ 196 197 /****************************************************************************** 198 * This function performs initializations that are specific to NON-SECURE state 199 * and updates the cpu context specified by 'ctx'. 200 *****************************************************************************/ 201 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 202 { 203 u_register_t scr_el3; 204 el3_state_t *state; 205 206 state = get_el3state_ctx(ctx); 207 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 208 209 /* SCR_NS: Set the NS bit */ 210 scr_el3 |= SCR_NS_BIT; 211 212 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 213 if (is_feat_mte2_supported()) { 214 scr_el3 |= SCR_ATA_BIT; 215 } 216 217 #if !CTX_INCLUDE_PAUTH_REGS 218 /* 219 * Pointer Authentication feature, if present, is always enabled by default 220 * for Non secure lower exception levels. We do not have an explicit 221 * flag to set it. 222 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 223 * exception levels of secure and realm worlds. 224 * 225 * To prevent the leakage between the worlds during world switch, 226 * we enable it only for the non-secure world. 227 * 228 * If the Secure/realm world wants to use pointer authentication, 229 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 230 * it will be enabled globally for all the contexts. 231 * 232 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 233 * other than EL3 234 * 235 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 236 * than EL3 237 */ 238 if (is_armv8_3_pauth_present()) { 239 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 240 } 241 #endif /* CTX_INCLUDE_PAUTH_REGS */ 242 243 #if HANDLE_EA_EL3_FIRST_NS 244 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 245 scr_el3 |= SCR_EA_BIT; 246 #endif 247 248 #if RAS_TRAP_NS_ERR_REC_ACCESS 249 /* 250 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 251 * and RAS ERX registers from EL1 and EL2(from any security state) 252 * are trapped to EL3. 253 * Set here to trap only for NS EL1/EL2 254 */ 255 scr_el3 |= SCR_TERR_BIT; 256 #endif 257 258 /* CSV2 version 2 and above */ 259 if (is_feat_csv2_2_supported()) { 260 /* Enable access to the SCXTNUM_ELx registers. */ 261 scr_el3 |= SCR_EnSCXT_BIT; 262 } 263 264 #ifdef IMAGE_BL31 265 /* 266 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 267 * indicated by the interrupt routing model for BL31. 268 */ 269 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 270 #endif 271 272 if (is_feat_the_supported()) { 273 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 274 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 275 */ 276 scr_el3 |= SCR_RCWMASKEn_BIT; 277 } 278 279 if (is_feat_sctlr2_supported()) { 280 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 281 * SCTLR2_ELx registers. 282 */ 283 scr_el3 |= SCR_SCTLR2En_BIT; 284 } 285 286 if (is_feat_d128_supported()) { 287 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 288 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 289 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 290 */ 291 scr_el3 |= SCR_D128En_BIT; 292 } 293 294 if (is_feat_fpmr_supported()) { 295 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 296 * register. 297 */ 298 scr_el3 |= SCR_EnFPM_BIT; 299 } 300 301 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 302 303 /* Initialize EL2 context registers */ 304 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 305 306 /* 307 * Initialize SCTLR_EL2 context register with reset value. 308 */ 309 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 310 311 if (is_feat_hcx_supported()) { 312 /* 313 * Initialize register HCRX_EL2 with its init value. 314 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 315 * chance that this can lead to unexpected behavior in lower 316 * ELs that have not been updated since the introduction of 317 * this feature if not properly initialized, especially when 318 * it comes to those bits that enable/disable traps. 319 */ 320 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 321 HCRX_EL2_INIT_VAL); 322 } 323 324 if (is_feat_fgt_supported()) { 325 /* 326 * Initialize HFG*_EL2 registers with a default value so legacy 327 * systems unaware of FEAT_FGT do not get trapped due to their lack 328 * of initialization for this feature. 329 */ 330 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 331 HFGITR_EL2_INIT_VAL); 332 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 333 HFGRTR_EL2_INIT_VAL); 334 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 335 HFGWTR_EL2_INIT_VAL); 336 } 337 #else 338 /* Initialize EL1 context registers */ 339 setup_el1_context(ctx, ep); 340 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 341 342 manage_extensions_nonsecure(ctx); 343 } 344 345 /******************************************************************************* 346 * The following function performs initialization of the cpu_context 'ctx' 347 * for first use that is common to all security states, and sets the 348 * initial entrypoint state as specified by the entry_point_info structure. 349 * 350 * The EE and ST attributes are used to configure the endianness and secure 351 * timer availability for the new execution context. 352 ******************************************************************************/ 353 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 354 { 355 u_register_t scr_el3; 356 u_register_t mdcr_el3; 357 el3_state_t *state; 358 gp_regs_t *gp_regs; 359 360 state = get_el3state_ctx(ctx); 361 362 /* Clear any residual register values from the context */ 363 zeromem(ctx, sizeof(*ctx)); 364 365 /* 366 * The lower-EL context is zeroed so that no stale values leak to a world. 367 * It is assumed that an all-zero lower-EL context is good enough for it 368 * to boot correctly. However, there are very few registers where this 369 * is not true and some values need to be recreated. 370 */ 371 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 372 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 373 374 /* 375 * These bits are set in the gicv3 driver. Losing them (especially the 376 * SRE bit) is problematic for all worlds. Henceforth recreate them. 377 */ 378 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 379 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 380 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 381 382 /* 383 * The actlr_el2 register can be initialized in platform's reset handler 384 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 385 */ 386 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 387 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 388 389 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 390 scr_el3 = SCR_RESET_VAL; 391 392 /* 393 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 394 * EL2, EL1 and EL0 are not trapped to EL3. 395 * 396 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 397 * EL2, EL1 and EL0 are not trapped to EL3. 398 * 399 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 400 * both Security states and both Execution states. 401 * 402 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 403 * Non-secure memory. 404 */ 405 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 406 407 scr_el3 |= SCR_SIF_BIT; 408 409 /* 410 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 411 * Exception level as specified by SPSR. 412 */ 413 if (GET_RW(ep->spsr) == MODE_RW_64) { 414 scr_el3 |= SCR_RW_BIT; 415 } 416 417 /* 418 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 419 * Secure timer registers to EL3, from AArch64 state only, if specified 420 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 421 * bit always behaves as 1 (i.e. secure physical timer register access 422 * is not trapped) 423 */ 424 if (EP_GET_ST(ep->h.attr) != 0U) { 425 scr_el3 |= SCR_ST_BIT; 426 } 427 428 /* 429 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 430 * SCR_EL3.HXEn. 431 */ 432 if (is_feat_hcx_supported()) { 433 scr_el3 |= SCR_HXEn_BIT; 434 } 435 436 /* 437 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 438 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 439 * SCR_EL3.EnAS0. 440 */ 441 if (is_feat_ls64_accdata_supported()) { 442 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 443 } 444 445 /* 446 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 447 * registers are trapped to EL3. 448 */ 449 if (is_feat_rng_trap_supported()) { 450 scr_el3 |= SCR_TRNDR_BIT; 451 } 452 453 #if FAULT_INJECTION_SUPPORT 454 /* Enable fault injection from lower ELs */ 455 scr_el3 |= SCR_FIEN_BIT; 456 #endif 457 458 #if CTX_INCLUDE_PAUTH_REGS 459 /* 460 * Enable Pointer Authentication globally for all the worlds. 461 * 462 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 463 * other than EL3 464 * 465 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 466 * than EL3 467 */ 468 if (is_armv8_3_pauth_present()) { 469 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 470 } 471 #endif /* CTX_INCLUDE_PAUTH_REGS */ 472 473 /* 474 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 475 */ 476 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 477 scr_el3 |= SCR_TCR2EN_BIT; 478 } 479 480 /* 481 * SCR_EL3.PIEN: Enable permission indirection and overlay 482 * registers for AArch64 if present. 483 */ 484 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 485 scr_el3 |= SCR_PIEN_BIT; 486 } 487 488 /* 489 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 490 */ 491 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 492 scr_el3 |= SCR_GCSEn_BIT; 493 } 494 495 /* 496 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 497 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 498 * next mode is Hyp. 499 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 500 * same conditions as HVC instructions and when the processor supports 501 * ARMv8.6-FGT. 502 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 503 * CNTPOFF_EL2 register under the same conditions as HVC instructions 504 * and when the processor supports ECV. 505 */ 506 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 507 || ((GET_RW(ep->spsr) != MODE_RW_64) 508 && (GET_M32(ep->spsr) == MODE32_hyp))) { 509 scr_el3 |= SCR_HCE_BIT; 510 511 if (is_feat_fgt_supported()) { 512 scr_el3 |= SCR_FGTEN_BIT; 513 } 514 515 if (is_feat_ecv_supported()) { 516 scr_el3 |= SCR_ECVEN_BIT; 517 } 518 } 519 520 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 521 if (is_feat_twed_supported()) { 522 /* Set delay in SCR_EL3 */ 523 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 524 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 525 << SCR_TWEDEL_SHIFT); 526 527 /* Enable WFE delay */ 528 scr_el3 |= SCR_TWEDEn_BIT; 529 } 530 531 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 532 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 533 if (is_feat_sel2_supported()) { 534 scr_el3 |= SCR_EEL2_BIT; 535 } 536 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 537 538 /* 539 * Populate EL3 state so that we've the right context 540 * before doing ERET 541 */ 542 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 543 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 544 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 545 546 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 547 mdcr_el3 = MDCR_EL3_RESET_VAL; 548 549 /* --------------------------------------------------------------------- 550 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 551 * Some fields are architecturally UNKNOWN on reset. 552 * 553 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 554 * Debug exceptions, other than Breakpoint Instruction exceptions, are 555 * disabled from all ELs in Secure state. 556 * 557 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 558 * privileged debug from S-EL1. 559 * 560 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 561 * access to the powerdown debug registers do not trap to EL3. 562 * 563 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 564 * debug registers, other than those registers that are controlled by 565 * MDCR_EL3.TDOSA. 566 */ 567 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 568 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 569 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 570 571 #if IMAGE_BL31 572 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 573 if (is_feat_trf_supported()) { 574 trf_enable(ctx); 575 } 576 577 pmuv3_enable(ctx); 578 #endif /* IMAGE_BL31 */ 579 580 /* 581 * Store the X0-X7 value from the entrypoint into the context 582 * Use memcpy as we are in control of the layout of the structures 583 */ 584 gp_regs = get_gpregs_ctx(ctx); 585 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 586 } 587 588 /******************************************************************************* 589 * Context management library initialization routine. This library is used by 590 * runtime services to share pointers to 'cpu_context' structures for secure 591 * non-secure and realm states. Management of the structures and their associated 592 * memory is not done by the context management library e.g. the PSCI service 593 * manages the cpu context used for entry from and exit to the non-secure state. 594 * The Secure payload dispatcher service manages the context(s) corresponding to 595 * the secure state. It also uses this library to get access to the non-secure 596 * state cpu context pointers. 597 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 598 * which will be used for programming an entry into a lower EL. The same context 599 * will be used to save state upon exception entry from that EL. 600 ******************************************************************************/ 601 void __init cm_init(void) 602 { 603 /* 604 * The context management library has only global data to initialize, but 605 * that will be done when the BSS is zeroed out. 606 */ 607 } 608 609 /******************************************************************************* 610 * This is the high-level function used to initialize the cpu_context 'ctx' for 611 * first use. It performs initializations that are common to all security states 612 * and initializations specific to the security state specified in 'ep' 613 ******************************************************************************/ 614 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 615 { 616 unsigned int security_state; 617 618 assert(ctx != NULL); 619 620 /* 621 * Perform initializations that are common 622 * to all security states 623 */ 624 setup_context_common(ctx, ep); 625 626 security_state = GET_SECURITY_STATE(ep->h.attr); 627 628 /* Perform security state specific initializations */ 629 switch (security_state) { 630 case SECURE: 631 setup_secure_context(ctx, ep); 632 break; 633 #if ENABLE_RME 634 case REALM: 635 setup_realm_context(ctx, ep); 636 break; 637 #endif 638 case NON_SECURE: 639 setup_ns_context(ctx, ep); 640 break; 641 default: 642 ERROR("Invalid security state\n"); 643 panic(); 644 break; 645 } 646 } 647 648 /******************************************************************************* 649 * Enable architecture extensions for EL3 execution. This function only updates 650 * registers in-place which are expected to either never change or be 651 * overwritten by el3_exit. 652 ******************************************************************************/ 653 #if IMAGE_BL31 654 void cm_manage_extensions_el3(void) 655 { 656 if (is_feat_amu_supported()) { 657 amu_init_el3(); 658 } 659 660 if (is_feat_sme_supported()) { 661 sme_init_el3(); 662 } 663 664 pmuv3_init_el3(); 665 } 666 #endif /* IMAGE_BL31 */ 667 668 /****************************************************************************** 669 * Function to initialise the registers with the RESET values in the context 670 * memory, which are maintained per world. 671 ******************************************************************************/ 672 #if IMAGE_BL31 673 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 674 { 675 /* 676 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 677 * 678 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 679 * by Advanced SIMD, floating-point or SVE instructions (if 680 * implemented) do not trap to EL3. 681 * 682 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 683 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 684 */ 685 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 686 687 per_world_ctx->ctx_cptr_el3 = cptr_el3; 688 689 /* 690 * Initialize MPAM3_EL3 to its default reset value 691 * 692 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 693 * all lower ELn MPAM3_EL3 register access to, trap to EL3 694 */ 695 696 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 697 } 698 #endif /* IMAGE_BL31 */ 699 700 /******************************************************************************* 701 * Initialise per_world_context for Non-Secure world. 702 * This function enables the architecture extensions, which have same value 703 * across the cores for the non-secure world. 704 ******************************************************************************/ 705 #if IMAGE_BL31 706 void manage_extensions_nonsecure_per_world(void) 707 { 708 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 709 710 if (is_feat_sme_supported()) { 711 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 712 } 713 714 if (is_feat_sve_supported()) { 715 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 716 } 717 718 if (is_feat_amu_supported()) { 719 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 720 } 721 722 if (is_feat_sys_reg_trace_supported()) { 723 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 724 } 725 726 if (is_feat_mpam_supported()) { 727 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 728 } 729 730 if (is_feat_fpmr_supported()) { 731 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 732 } 733 } 734 #endif /* IMAGE_BL31 */ 735 736 /******************************************************************************* 737 * Initialise per_world_context for Secure world. 738 * This function enables the architecture extensions, which have same value 739 * across the cores for the secure world. 740 ******************************************************************************/ 741 static void manage_extensions_secure_per_world(void) 742 { 743 #if IMAGE_BL31 744 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 745 746 if (is_feat_sme_supported()) { 747 748 if (ENABLE_SME_FOR_SWD) { 749 /* 750 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 751 * SME, SVE, and FPU/SIMD context properly managed. 752 */ 753 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 754 } else { 755 /* 756 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 757 * world can safely use the associated registers. 758 */ 759 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 760 } 761 } 762 if (is_feat_sve_supported()) { 763 if (ENABLE_SVE_FOR_SWD) { 764 /* 765 * Enable SVE and FPU in secure context, SPM must ensure 766 * that the SVE and FPU register contexts are properly managed. 767 */ 768 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 769 } else { 770 /* 771 * Disable SVE and FPU in secure context so non-secure world 772 * can safely use them. 773 */ 774 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 775 } 776 } 777 778 /* NS can access this but Secure shouldn't */ 779 if (is_feat_sys_reg_trace_supported()) { 780 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 781 } 782 783 has_secure_perworld_init = true; 784 #endif /* IMAGE_BL31 */ 785 } 786 787 /******************************************************************************* 788 * Enable architecture extensions on first entry to Non-secure world. 789 ******************************************************************************/ 790 static void manage_extensions_nonsecure(cpu_context_t *ctx) 791 { 792 #if IMAGE_BL31 793 if (is_feat_amu_supported()) { 794 amu_enable(ctx); 795 } 796 797 if (is_feat_sme_supported()) { 798 sme_enable(ctx); 799 } 800 801 if (is_feat_fgt2_supported()) { 802 fgt2_enable(ctx); 803 } 804 805 if (is_feat_debugv8p9_supported()) { 806 debugv8p9_extended_bp_wp_enable(ctx); 807 } 808 809 /* 810 * SPE, TRBE, and BRBE have multi-field enables that affect which world 811 * they apply to. Despite this, it is useful to ignore these for 812 * simplicity in determining the feature's per world enablement status. 813 * This is only possible when context is written per-world. Relied on 814 * by SMCCC_ARCH_FEATURE_AVAILABILITY 815 */ 816 if (is_feat_spe_supported()) { 817 spe_enable(ctx); 818 } 819 820 if (is_feat_trbe_supported()) { 821 trbe_enable(ctx); 822 } 823 824 if (is_feat_brbe_supported()) { 825 brbe_enable(ctx); 826 } 827 #endif /* IMAGE_BL31 */ 828 } 829 830 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 831 static __unused void enable_pauth_el2(void) 832 { 833 u_register_t hcr_el2 = read_hcr_el2(); 834 /* 835 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 836 * accessing key registers or using pointer authentication instructions 837 * from lower ELs. 838 */ 839 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 840 841 write_hcr_el2(hcr_el2); 842 } 843 844 #if INIT_UNUSED_NS_EL2 845 /******************************************************************************* 846 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 847 * world when EL2 is empty and unused. 848 ******************************************************************************/ 849 static void manage_extensions_nonsecure_el2_unused(void) 850 { 851 #if IMAGE_BL31 852 if (is_feat_spe_supported()) { 853 spe_init_el2_unused(); 854 } 855 856 if (is_feat_amu_supported()) { 857 amu_init_el2_unused(); 858 } 859 860 if (is_feat_mpam_supported()) { 861 mpam_init_el2_unused(); 862 } 863 864 if (is_feat_trbe_supported()) { 865 trbe_init_el2_unused(); 866 } 867 868 if (is_feat_sys_reg_trace_supported()) { 869 sys_reg_trace_init_el2_unused(); 870 } 871 872 if (is_feat_trf_supported()) { 873 trf_init_el2_unused(); 874 } 875 876 pmuv3_init_el2_unused(); 877 878 if (is_feat_sve_supported()) { 879 sve_init_el2_unused(); 880 } 881 882 if (is_feat_sme_supported()) { 883 sme_init_el2_unused(); 884 } 885 886 if (is_feat_mops_supported()) { 887 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 888 } 889 890 #if ENABLE_PAUTH 891 enable_pauth_el2(); 892 #endif /* ENABLE_PAUTH */ 893 #endif /* IMAGE_BL31 */ 894 } 895 #endif /* INIT_UNUSED_NS_EL2 */ 896 897 /******************************************************************************* 898 * Enable architecture extensions on first entry to Secure world. 899 ******************************************************************************/ 900 static void manage_extensions_secure(cpu_context_t *ctx) 901 { 902 #if IMAGE_BL31 903 if (is_feat_sme_supported()) { 904 if (ENABLE_SME_FOR_SWD) { 905 /* 906 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 907 * must ensure SME, SVE, and FPU/SIMD context properly managed. 908 */ 909 sme_init_el3(); 910 sme_enable(ctx); 911 } else { 912 /* 913 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 914 * world can safely use the associated registers. 915 */ 916 sme_disable(ctx); 917 } 918 } 919 920 /* 921 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 922 * sysreg access can. In case the EL1 controls leave them active on 923 * context switch, we want the owning security state to be NS so Secure 924 * can't be DOSed. 925 */ 926 if (is_feat_spe_supported()) { 927 spe_disable(ctx); 928 } 929 930 if (is_feat_trbe_supported()) { 931 trbe_disable(ctx); 932 } 933 #endif /* IMAGE_BL31 */ 934 } 935 936 #if !IMAGE_BL1 937 /******************************************************************************* 938 * The following function initializes the cpu_context for a CPU specified by 939 * its `cpu_idx` for first use, and sets the initial entrypoint state as 940 * specified by the entry_point_info structure. 941 ******************************************************************************/ 942 void cm_init_context_by_index(unsigned int cpu_idx, 943 const entry_point_info_t *ep) 944 { 945 cpu_context_t *ctx; 946 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 947 cm_setup_context(ctx, ep); 948 } 949 #endif /* !IMAGE_BL1 */ 950 951 /******************************************************************************* 952 * The following function initializes the cpu_context for the current CPU 953 * for first use, and sets the initial entrypoint state as specified by the 954 * entry_point_info structure. 955 ******************************************************************************/ 956 void cm_init_my_context(const entry_point_info_t *ep) 957 { 958 cpu_context_t *ctx; 959 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 960 cm_setup_context(ctx, ep); 961 } 962 963 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 964 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 965 { 966 #if INIT_UNUSED_NS_EL2 967 u_register_t hcr_el2 = HCR_RESET_VAL; 968 u_register_t mdcr_el2; 969 u_register_t scr_el3; 970 971 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 972 973 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 974 if ((scr_el3 & SCR_RW_BIT) != 0U) { 975 hcr_el2 |= HCR_RW_BIT; 976 } 977 978 write_hcr_el2(hcr_el2); 979 980 /* 981 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 982 * All fields have architecturally UNKNOWN reset values. 983 */ 984 write_cptr_el2(CPTR_EL2_RESET_VAL); 985 986 /* 987 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 988 * reset and are set to zero except for field(s) listed below. 989 * 990 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 991 * Non-secure EL0 and EL1 accesses to the physical timer registers. 992 * 993 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 994 * Non-secure EL0 and EL1 accesses to the physical counter registers. 995 */ 996 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 997 998 /* 999 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1000 * UNKNOWN value. 1001 */ 1002 write_cntvoff_el2(0); 1003 1004 /* 1005 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1006 * respectively. 1007 */ 1008 write_vpidr_el2(read_midr_el1()); 1009 write_vmpidr_el2(read_mpidr_el1()); 1010 1011 /* 1012 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1013 * 1014 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1015 * translation is disabled, cache maintenance operations depend on the 1016 * VMID. 1017 * 1018 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1019 * disabled. 1020 */ 1021 write_vttbr_el2(VTTBR_RESET_VAL & 1022 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1023 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1024 1025 /* 1026 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1027 * Some fields are architecturally UNKNOWN on reset. 1028 * 1029 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1030 * register accesses to the Debug ROM registers are not trapped to EL2. 1031 * 1032 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1033 * accesses to the powerdown debug registers are not trapped to EL2. 1034 * 1035 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1036 * debug registers do not trap to EL2. 1037 * 1038 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1039 * EL2. 1040 */ 1041 mdcr_el2 = MDCR_EL2_RESET_VAL & 1042 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1043 MDCR_EL2_TDE_BIT); 1044 1045 write_mdcr_el2(mdcr_el2); 1046 1047 /* 1048 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1049 * 1050 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1051 * EL1 accesses to System registers do not trap to EL2. 1052 */ 1053 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1054 1055 /* 1056 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1057 * reset. 1058 * 1059 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1060 * and prevent timer interrupts. 1061 */ 1062 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1063 1064 manage_extensions_nonsecure_el2_unused(); 1065 #endif /* INIT_UNUSED_NS_EL2 */ 1066 } 1067 1068 /******************************************************************************* 1069 * Prepare the CPU system registers for first entry into realm, secure, or 1070 * normal world. 1071 * 1072 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1073 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1074 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1075 * For all entries, the EL1 registers are initialized from the cpu_context 1076 ******************************************************************************/ 1077 void cm_prepare_el3_exit(uint32_t security_state) 1078 { 1079 u_register_t sctlr_el2, scr_el3; 1080 cpu_context_t *ctx = cm_get_context(security_state); 1081 1082 assert(ctx != NULL); 1083 1084 if (security_state == NON_SECURE) { 1085 uint64_t el2_implemented = el_implemented(2); 1086 1087 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1088 CTX_SCR_EL3); 1089 1090 if (el2_implemented != EL_IMPL_NONE) { 1091 1092 /* 1093 * If context is not being used for EL2, initialize 1094 * HCRX_EL2 with its init value here. 1095 */ 1096 if (is_feat_hcx_supported()) { 1097 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1098 } 1099 1100 /* 1101 * Initialize Fine-grained trap registers introduced 1102 * by FEAT_FGT so all traps are initially disabled when 1103 * switching to EL2 or a lower EL, preventing undesired 1104 * behavior. 1105 */ 1106 if (is_feat_fgt_supported()) { 1107 /* 1108 * Initialize HFG*_EL2 registers with a default 1109 * value so legacy systems unaware of FEAT_FGT 1110 * do not get trapped due to their lack of 1111 * initialization for this feature. 1112 */ 1113 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1114 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1115 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1116 } 1117 1118 /* Condition to ensure EL2 is being used. */ 1119 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1120 /* Initialize SCTLR_EL2 register with reset value. */ 1121 sctlr_el2 = SCTLR_EL2_RES1; 1122 1123 /* 1124 * If workaround of errata 764081 for Cortex-A75 1125 * is used then set SCTLR_EL2.IESB to enable 1126 * Implicit Error Synchronization Barrier. 1127 */ 1128 if (errata_a75_764081_applies()) { 1129 sctlr_el2 |= SCTLR_IESB_BIT; 1130 } 1131 1132 write_sctlr_el2(sctlr_el2); 1133 } else { 1134 /* 1135 * (scr_el3 & SCR_HCE_BIT==0) 1136 * EL2 implemented but unused. 1137 */ 1138 init_nonsecure_el2_unused(ctx); 1139 } 1140 } 1141 } 1142 #if (!CTX_INCLUDE_EL2_REGS) 1143 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1144 cm_el1_sysregs_context_restore(security_state); 1145 #endif 1146 cm_set_next_eret_context(security_state); 1147 } 1148 1149 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1150 1151 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1152 { 1153 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1154 if (is_feat_amu_supported()) { 1155 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1156 } 1157 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1158 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1159 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1160 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1161 } 1162 1163 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1164 { 1165 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1166 if (is_feat_amu_supported()) { 1167 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1168 } 1169 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1170 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1171 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1172 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1173 } 1174 1175 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1176 { 1177 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1178 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1179 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1180 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1181 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1182 } 1183 1184 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1185 { 1186 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1187 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1188 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1189 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1190 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1191 } 1192 1193 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1194 { 1195 u_register_t mpam_idr = read_mpamidr_el1(); 1196 1197 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1198 1199 /* 1200 * The context registers that we intend to save would be part of the 1201 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1202 */ 1203 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1204 return; 1205 } 1206 1207 /* 1208 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1209 * MPAMIDR_HAS_HCR_BIT == 1. 1210 */ 1211 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1212 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1213 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1214 1215 /* 1216 * The number of MPAMVPM registers is implementation defined, their 1217 * number is stored in the MPAMIDR_EL1 register. 1218 */ 1219 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1220 case 7: 1221 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1222 __fallthrough; 1223 case 6: 1224 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1225 __fallthrough; 1226 case 5: 1227 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1228 __fallthrough; 1229 case 4: 1230 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1231 __fallthrough; 1232 case 3: 1233 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1234 __fallthrough; 1235 case 2: 1236 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1237 __fallthrough; 1238 case 1: 1239 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1240 break; 1241 } 1242 } 1243 1244 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1245 { 1246 u_register_t mpam_idr = read_mpamidr_el1(); 1247 1248 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1249 1250 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1251 return; 1252 } 1253 1254 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1255 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1256 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1257 1258 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1259 case 7: 1260 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1261 __fallthrough; 1262 case 6: 1263 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1264 __fallthrough; 1265 case 5: 1266 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1267 __fallthrough; 1268 case 4: 1269 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1270 __fallthrough; 1271 case 3: 1272 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1273 __fallthrough; 1274 case 2: 1275 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1276 __fallthrough; 1277 case 1: 1278 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1279 break; 1280 } 1281 } 1282 1283 /* --------------------------------------------------------------------------- 1284 * The following registers are not added: 1285 * ICH_AP0R<n>_EL2 1286 * ICH_AP1R<n>_EL2 1287 * ICH_LR<n>_EL2 1288 * 1289 * NOTE: For a system with S-EL2 present but not enabled, accessing 1290 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1291 * SCR_EL3.NS = 1 before accessing this register. 1292 * --------------------------------------------------------------------------- 1293 */ 1294 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1295 { 1296 u_register_t scr_el3 = read_scr_el3(); 1297 1298 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1299 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1300 #else 1301 write_scr_el3(scr_el3 | SCR_NS_BIT); 1302 isb(); 1303 1304 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1305 1306 write_scr_el3(scr_el3); 1307 isb(); 1308 #endif 1309 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1310 1311 if (errata_ich_vmcr_el2_applies()) { 1312 if (security_state == SECURE) { 1313 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1314 } else { 1315 write_scr_el3(scr_el3 | SCR_NS_BIT); 1316 } 1317 isb(); 1318 } 1319 1320 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1321 1322 if (errata_ich_vmcr_el2_applies()) { 1323 write_scr_el3(scr_el3); 1324 isb(); 1325 } 1326 } 1327 1328 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1329 { 1330 u_register_t scr_el3 = read_scr_el3(); 1331 1332 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1333 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1334 #else 1335 write_scr_el3(scr_el3 | SCR_NS_BIT); 1336 isb(); 1337 1338 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1339 1340 write_scr_el3(scr_el3); 1341 isb(); 1342 #endif 1343 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1344 1345 if (errata_ich_vmcr_el2_applies()) { 1346 if (security_state == SECURE) { 1347 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1348 } else { 1349 write_scr_el3(scr_el3 | SCR_NS_BIT); 1350 } 1351 isb(); 1352 } 1353 1354 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1355 1356 if (errata_ich_vmcr_el2_applies()) { 1357 write_scr_el3(scr_el3); 1358 isb(); 1359 } 1360 } 1361 1362 /* ----------------------------------------------------- 1363 * The following registers are not added: 1364 * AMEVCNTVOFF0<n>_EL2 1365 * AMEVCNTVOFF1<n>_EL2 1366 * ----------------------------------------------------- 1367 */ 1368 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1369 { 1370 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1371 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1372 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1373 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1374 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1375 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1376 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1377 if (CTX_INCLUDE_AARCH32_REGS) { 1378 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1379 } 1380 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1381 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1382 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1383 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1384 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1385 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1386 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1387 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1388 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1389 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1390 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1391 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1392 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1393 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1394 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1395 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1396 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1397 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1398 1399 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1400 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1401 } 1402 1403 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1404 { 1405 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1406 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1407 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1408 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1409 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1410 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1411 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1412 if (CTX_INCLUDE_AARCH32_REGS) { 1413 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1414 } 1415 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1416 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1417 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1418 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1419 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1420 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1421 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1422 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1423 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1424 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1425 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1426 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1427 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1428 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1429 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1430 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1431 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1432 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1433 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1434 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1435 } 1436 1437 /******************************************************************************* 1438 * Save EL2 sysreg context 1439 ******************************************************************************/ 1440 void cm_el2_sysregs_context_save(uint32_t security_state) 1441 { 1442 cpu_context_t *ctx; 1443 el2_sysregs_t *el2_sysregs_ctx; 1444 1445 ctx = cm_get_context(security_state); 1446 assert(ctx != NULL); 1447 1448 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1449 1450 el2_sysregs_context_save_common(el2_sysregs_ctx); 1451 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1452 1453 if (is_feat_mte2_supported()) { 1454 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1455 } 1456 1457 if (is_feat_mpam_supported()) { 1458 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1459 } 1460 1461 if (is_feat_fgt_supported()) { 1462 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1463 } 1464 1465 if (is_feat_fgt2_supported()) { 1466 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1467 } 1468 1469 if (is_feat_ecv_v2_supported()) { 1470 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1471 } 1472 1473 if (is_feat_vhe_supported()) { 1474 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1475 read_contextidr_el2()); 1476 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1477 } 1478 1479 if (is_feat_ras_supported()) { 1480 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1481 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1482 } 1483 1484 if (is_feat_nv2_supported()) { 1485 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1486 } 1487 1488 if (is_feat_trf_supported()) { 1489 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1490 } 1491 1492 if (is_feat_csv2_2_supported()) { 1493 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1494 read_scxtnum_el2()); 1495 } 1496 1497 if (is_feat_hcx_supported()) { 1498 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1499 } 1500 1501 if (is_feat_tcr2_supported()) { 1502 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1503 } 1504 1505 if (is_feat_sxpie_supported()) { 1506 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1507 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1508 } 1509 1510 if (is_feat_sxpoe_supported()) { 1511 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1512 } 1513 1514 if (is_feat_s2pie_supported()) { 1515 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1516 } 1517 1518 if (is_feat_gcs_supported()) { 1519 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1520 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1521 } 1522 1523 if (is_feat_sctlr2_supported()) { 1524 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1525 } 1526 } 1527 1528 /******************************************************************************* 1529 * Restore EL2 sysreg context 1530 ******************************************************************************/ 1531 void cm_el2_sysregs_context_restore(uint32_t security_state) 1532 { 1533 cpu_context_t *ctx; 1534 el2_sysregs_t *el2_sysregs_ctx; 1535 1536 ctx = cm_get_context(security_state); 1537 assert(ctx != NULL); 1538 1539 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1540 1541 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1542 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1543 1544 if (is_feat_mte2_supported()) { 1545 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1546 } 1547 1548 if (is_feat_mpam_supported()) { 1549 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1550 } 1551 1552 if (is_feat_fgt_supported()) { 1553 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1554 } 1555 1556 if (is_feat_fgt2_supported()) { 1557 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1558 } 1559 1560 if (is_feat_ecv_v2_supported()) { 1561 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1562 } 1563 1564 if (is_feat_vhe_supported()) { 1565 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1566 contextidr_el2)); 1567 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1568 } 1569 1570 if (is_feat_ras_supported()) { 1571 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1572 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1573 } 1574 1575 if (is_feat_nv2_supported()) { 1576 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1577 } 1578 1579 if (is_feat_trf_supported()) { 1580 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1581 } 1582 1583 if (is_feat_csv2_2_supported()) { 1584 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1585 scxtnum_el2)); 1586 } 1587 1588 if (is_feat_hcx_supported()) { 1589 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1590 } 1591 1592 if (is_feat_tcr2_supported()) { 1593 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1594 } 1595 1596 if (is_feat_sxpie_supported()) { 1597 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1598 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1599 } 1600 1601 if (is_feat_sxpoe_supported()) { 1602 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1603 } 1604 1605 if (is_feat_s2pie_supported()) { 1606 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1607 } 1608 1609 if (is_feat_gcs_supported()) { 1610 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1611 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1612 } 1613 1614 if (is_feat_sctlr2_supported()) { 1615 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1616 } 1617 } 1618 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1619 1620 #if IMAGE_BL31 1621 /********************************************************************************* 1622 * This function allows Architecture features asymmetry among cores. 1623 * TF-A assumes that all the cores in the platform has architecture feature parity 1624 * and hence the context is setup on different core (e.g. primary sets up the 1625 * context for secondary cores).This assumption may not be true for systems where 1626 * cores are not conforming to same Arch version or there is CPU Erratum which 1627 * requires certain feature to be be disabled only on a given core. 1628 * 1629 * This function is called on secondary cores to override any disparity in context 1630 * setup by primary, this would be called during warmboot path. 1631 *********************************************************************************/ 1632 void cm_handle_asymmetric_features(void) 1633 { 1634 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1635 1636 assert(ctx != NULL); 1637 1638 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1639 if (is_feat_spe_supported()) { 1640 spe_enable(ctx); 1641 } else { 1642 spe_disable(ctx); 1643 } 1644 #endif 1645 1646 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1647 if (check_if_affected_core() == ERRATA_APPLIES) { 1648 if (is_feat_trbe_supported()) { 1649 trbe_disable(ctx); 1650 } 1651 } 1652 #endif 1653 1654 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1655 el3_state_t *el3_state = get_el3state_ctx(ctx); 1656 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1657 1658 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1659 tcr2_enable(ctx); 1660 } else { 1661 tcr2_disable(ctx); 1662 } 1663 #endif 1664 1665 } 1666 #endif 1667 1668 /******************************************************************************* 1669 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1670 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1671 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1672 * cm_prepare_el3_exit function. 1673 ******************************************************************************/ 1674 void cm_prepare_el3_exit_ns(void) 1675 { 1676 #if IMAGE_BL31 1677 /* 1678 * Check and handle Architecture feature asymmetry among cores. 1679 * 1680 * In warmboot path secondary cores context is initialized on core which 1681 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1682 * it in this function call. 1683 * For Symmetric cores this is an empty function. 1684 */ 1685 cm_handle_asymmetric_features(); 1686 #endif 1687 1688 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1689 #if ENABLE_ASSERTIONS 1690 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1691 assert(ctx != NULL); 1692 1693 /* Assert that EL2 is used. */ 1694 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1695 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1696 (el_implemented(2U) != EL_IMPL_NONE)); 1697 #endif /* ENABLE_ASSERTIONS */ 1698 1699 /* Restore EL2 sysreg contexts */ 1700 cm_el2_sysregs_context_restore(NON_SECURE); 1701 cm_set_next_eret_context(NON_SECURE); 1702 #else 1703 cm_prepare_el3_exit(NON_SECURE); 1704 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1705 } 1706 1707 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1708 /******************************************************************************* 1709 * The next set of six functions are used by runtime services to save and restore 1710 * EL1 context on the 'cpu_context' structure for the specified security state. 1711 ******************************************************************************/ 1712 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1713 { 1714 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1715 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1716 1717 #if (!ERRATA_SPECULATIVE_AT) 1718 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1719 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1720 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1721 1722 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1723 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1724 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1725 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1726 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1727 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1728 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1729 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1730 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1731 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1732 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1733 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1734 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1735 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1736 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1737 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1738 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1739 1740 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1741 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1742 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1743 1744 if (CTX_INCLUDE_AARCH32_REGS) { 1745 /* Save Aarch32 registers */ 1746 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1747 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1748 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1749 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1750 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1751 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1752 } 1753 1754 if (NS_TIMER_SWITCH) { 1755 /* Save NS Timer registers */ 1756 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1757 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1758 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1759 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1760 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1761 } 1762 1763 if (is_feat_mte2_supported()) { 1764 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1765 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1766 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1767 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1768 } 1769 1770 if (is_feat_ras_supported()) { 1771 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1772 } 1773 1774 if (is_feat_s1pie_supported()) { 1775 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1776 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1777 } 1778 1779 if (is_feat_s1poe_supported()) { 1780 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1781 } 1782 1783 if (is_feat_s2poe_supported()) { 1784 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1785 } 1786 1787 if (is_feat_tcr2_supported()) { 1788 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1789 } 1790 1791 if (is_feat_trf_supported()) { 1792 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1793 } 1794 1795 if (is_feat_csv2_2_supported()) { 1796 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1797 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1798 } 1799 1800 if (is_feat_gcs_supported()) { 1801 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1802 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1803 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1804 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1805 } 1806 1807 if (is_feat_the_supported()) { 1808 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1809 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1810 } 1811 1812 if (is_feat_sctlr2_supported()) { 1813 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1814 } 1815 1816 if (is_feat_ls64_accdata_supported()) { 1817 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1818 } 1819 } 1820 1821 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1822 { 1823 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1824 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1825 1826 #if (!ERRATA_SPECULATIVE_AT) 1827 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1828 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1829 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1830 1831 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1832 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1833 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1834 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1835 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1836 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1837 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1838 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1839 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1840 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1841 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1842 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1843 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1844 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1845 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1846 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1847 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1848 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1849 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1850 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1851 1852 if (CTX_INCLUDE_AARCH32_REGS) { 1853 /* Restore Aarch32 registers */ 1854 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1855 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1856 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1857 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1858 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1859 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1860 } 1861 1862 if (NS_TIMER_SWITCH) { 1863 /* Restore NS Timer registers */ 1864 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1865 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1866 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1867 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1868 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1869 } 1870 1871 if (is_feat_mte2_supported()) { 1872 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1873 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1874 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1875 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1876 } 1877 1878 if (is_feat_ras_supported()) { 1879 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1880 } 1881 1882 if (is_feat_s1pie_supported()) { 1883 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1884 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1885 } 1886 1887 if (is_feat_s1poe_supported()) { 1888 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1889 } 1890 1891 if (is_feat_s2poe_supported()) { 1892 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1893 } 1894 1895 if (is_feat_tcr2_supported()) { 1896 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1897 } 1898 1899 if (is_feat_trf_supported()) { 1900 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1901 } 1902 1903 if (is_feat_csv2_2_supported()) { 1904 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1905 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1906 } 1907 1908 if (is_feat_gcs_supported()) { 1909 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1910 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1911 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1912 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1913 } 1914 1915 if (is_feat_the_supported()) { 1916 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1917 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1918 } 1919 1920 if (is_feat_sctlr2_supported()) { 1921 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1922 } 1923 1924 if (is_feat_ls64_accdata_supported()) { 1925 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1926 } 1927 } 1928 1929 /******************************************************************************* 1930 * The next couple of functions are used by runtime services to save and restore 1931 * EL1 context on the 'cpu_context' structure for the specified security state. 1932 ******************************************************************************/ 1933 void cm_el1_sysregs_context_save(uint32_t security_state) 1934 { 1935 cpu_context_t *ctx; 1936 1937 ctx = cm_get_context(security_state); 1938 assert(ctx != NULL); 1939 1940 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1941 1942 #if IMAGE_BL31 1943 if (security_state == SECURE) 1944 PUBLISH_EVENT(cm_exited_secure_world); 1945 else 1946 PUBLISH_EVENT(cm_exited_normal_world); 1947 #endif 1948 } 1949 1950 void cm_el1_sysregs_context_restore(uint32_t security_state) 1951 { 1952 cpu_context_t *ctx; 1953 1954 ctx = cm_get_context(security_state); 1955 assert(ctx != NULL); 1956 1957 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1958 1959 #if IMAGE_BL31 1960 if (security_state == SECURE) 1961 PUBLISH_EVENT(cm_entering_secure_world); 1962 else 1963 PUBLISH_EVENT(cm_entering_normal_world); 1964 #endif 1965 } 1966 1967 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1968 1969 /******************************************************************************* 1970 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1971 * given security state with the given entrypoint 1972 ******************************************************************************/ 1973 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1974 { 1975 cpu_context_t *ctx; 1976 el3_state_t *state; 1977 1978 ctx = cm_get_context(security_state); 1979 assert(ctx != NULL); 1980 1981 /* Populate EL3 state so that ERET jumps to the correct entry */ 1982 state = get_el3state_ctx(ctx); 1983 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1984 } 1985 1986 /******************************************************************************* 1987 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1988 * pertaining to the given security state 1989 ******************************************************************************/ 1990 void cm_set_elr_spsr_el3(uint32_t security_state, 1991 uintptr_t entrypoint, uint32_t spsr) 1992 { 1993 cpu_context_t *ctx; 1994 el3_state_t *state; 1995 1996 ctx = cm_get_context(security_state); 1997 assert(ctx != NULL); 1998 1999 /* Populate EL3 state so that ERET jumps to the correct entry */ 2000 state = get_el3state_ctx(ctx); 2001 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2002 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2003 } 2004 2005 /******************************************************************************* 2006 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2007 * pertaining to the given security state using the value and bit position 2008 * specified in the parameters. It preserves all other bits. 2009 ******************************************************************************/ 2010 void cm_write_scr_el3_bit(uint32_t security_state, 2011 uint32_t bit_pos, 2012 uint32_t value) 2013 { 2014 cpu_context_t *ctx; 2015 el3_state_t *state; 2016 u_register_t scr_el3; 2017 2018 ctx = cm_get_context(security_state); 2019 assert(ctx != NULL); 2020 2021 /* Ensure that the bit position is a valid one */ 2022 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2023 2024 /* Ensure that the 'value' is only a bit wide */ 2025 assert(value <= 1U); 2026 2027 /* 2028 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2029 * and set it to its new value. 2030 */ 2031 state = get_el3state_ctx(ctx); 2032 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2033 scr_el3 &= ~(1UL << bit_pos); 2034 scr_el3 |= (u_register_t)value << bit_pos; 2035 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2036 } 2037 2038 /******************************************************************************* 2039 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2040 * given security state. 2041 ******************************************************************************/ 2042 u_register_t cm_get_scr_el3(uint32_t security_state) 2043 { 2044 cpu_context_t *ctx; 2045 el3_state_t *state; 2046 2047 ctx = cm_get_context(security_state); 2048 assert(ctx != NULL); 2049 2050 /* Populate EL3 state so that ERET jumps to the correct entry */ 2051 state = get_el3state_ctx(ctx); 2052 return read_ctx_reg(state, CTX_SCR_EL3); 2053 } 2054 2055 /******************************************************************************* 2056 * This function is used to program the context that's used for exception 2057 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2058 * the required security state 2059 ******************************************************************************/ 2060 void cm_set_next_eret_context(uint32_t security_state) 2061 { 2062 cpu_context_t *ctx; 2063 2064 ctx = cm_get_context(security_state); 2065 assert(ctx != NULL); 2066 2067 cm_set_next_context(ctx); 2068 } 2069