1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 if (is_feat_csv2_2_supported()) { 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 } 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 #if !CTX_INCLUDE_PAUTH_REGS 199 /* 200 * If the pointer authentication registers aren't saved during world 201 * switches the value of the registers can be leaked from the Secure to 202 * the Non-secure world. To prevent this, rather than enabling pointer 203 * authentication everywhere, we only enable it in the Non-secure world. 204 * 205 * If the Secure world wants to use pointer authentication, 206 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 207 */ 208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 209 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 210 211 /* Allow access to Allocation Tags when MTE is implemented. */ 212 scr_el3 |= SCR_ATA_BIT; 213 214 #if HANDLE_EA_EL3_FIRST_NS 215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 216 scr_el3 |= SCR_EA_BIT; 217 #endif 218 219 #if RAS_TRAP_NS_ERR_REC_ACCESS 220 /* 221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 222 * and RAS ERX registers from EL1 and EL2(from any security state) 223 * are trapped to EL3. 224 * Set here to trap only for NS EL1/EL2 225 * 226 */ 227 scr_el3 |= SCR_TERR_BIT; 228 #endif 229 230 if (is_feat_csv2_2_supported()) { 231 /* Enable access to the SCXTNUM_ELx registers. */ 232 scr_el3 |= SCR_EnSCXT_BIT; 233 } 234 235 #ifdef IMAGE_BL31 236 /* 237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 238 * indicated by the interrupt routing model for BL31. 239 */ 240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 241 #endif 242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 243 244 /* Initialize EL1 context registers */ 245 setup_el1_context(ctx, ep); 246 247 /* Initialize EL2 context registers */ 248 #if CTX_INCLUDE_EL2_REGS 249 250 /* 251 * Initialize SCTLR_EL2 context register using Endianness value 252 * taken from the entrypoint attribute. 253 */ 254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 255 sctlr_el2 |= SCTLR_EL2_RES1; 256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 257 sctlr_el2); 258 259 /* 260 * Program the ICC_SRE_EL2 to make sure the correct bits are set 261 * when restoring NS context. 262 */ 263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 266 icc_sre_el2); 267 268 /* 269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 270 * throw anyone off who expects this to be sensible. 271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 272 * unified with the proper PMU implementation 273 */ 274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 275 PMCR_EL0_N_MASK); 276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 277 278 if (is_feat_hcx_supported()) { 279 /* 280 * Initialize register HCRX_EL2 with its init value. 281 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 282 * chance that this can lead to unexpected behavior in lower 283 * ELs that have not been updated since the introduction of 284 * this feature if not properly initialized, especially when 285 * it comes to those bits that enable/disable traps. 286 */ 287 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 288 HCRX_EL2_INIT_VAL); 289 } 290 #endif /* CTX_INCLUDE_EL2_REGS */ 291 } 292 293 /******************************************************************************* 294 * The following function performs initialization of the cpu_context 'ctx' 295 * for first use that is common to all security states, and sets the 296 * initial entrypoint state as specified by the entry_point_info structure. 297 * 298 * The EE and ST attributes are used to configure the endianness and secure 299 * timer availability for the new execution context. 300 ******************************************************************************/ 301 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 302 { 303 u_register_t scr_el3; 304 el3_state_t *state; 305 gp_regs_t *gp_regs; 306 307 /* Clear any residual register values from the context */ 308 zeromem(ctx, sizeof(*ctx)); 309 310 /* 311 * SCR_EL3 was initialised during reset sequence in macro 312 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 313 * affect the next EL. 314 * 315 * The following fields are initially set to zero and then updated to 316 * the required value depending on the state of the SPSR_EL3 and the 317 * Security state and entrypoint attributes of the next EL. 318 */ 319 scr_el3 = read_scr(); 320 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 321 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 322 323 /* 324 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 325 * Exception level as specified by SPSR. 326 */ 327 if (GET_RW(ep->spsr) == MODE_RW_64) { 328 scr_el3 |= SCR_RW_BIT; 329 } 330 331 /* 332 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 333 * Secure timer registers to EL3, from AArch64 state only, if specified 334 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 335 * bit always behaves as 1 (i.e. secure physical timer register access 336 * is not trapped) 337 */ 338 if (EP_GET_ST(ep->h.attr) != 0U) { 339 scr_el3 |= SCR_ST_BIT; 340 } 341 342 /* 343 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 344 * SCR_EL3.HXEn. 345 */ 346 if (is_feat_hcx_supported()) { 347 scr_el3 |= SCR_HXEn_BIT; 348 } 349 350 /* 351 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 352 * registers are trapped to EL3. 353 */ 354 #if ENABLE_FEAT_RNG_TRAP 355 scr_el3 |= SCR_TRNDR_BIT; 356 #endif 357 358 #if FAULT_INJECTION_SUPPORT 359 /* Enable fault injection from lower ELs */ 360 scr_el3 |= SCR_FIEN_BIT; 361 #endif 362 363 /* 364 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 365 */ 366 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 367 scr_el3 |= SCR_TCR2EN_BIT; 368 } 369 370 /* 371 * SCR_EL3.PIEN: Enable permission indirection and overlay 372 * registers for AArch64 if present. 373 */ 374 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 375 scr_el3 |= SCR_PIEN_BIT; 376 } 377 378 /* 379 * CPTR_EL3 was initialized out of reset, copy that value to the 380 * context register. 381 */ 382 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 383 384 /* 385 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 386 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 387 * next mode is Hyp. 388 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 389 * same conditions as HVC instructions and when the processor supports 390 * ARMv8.6-FGT. 391 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 392 * CNTPOFF_EL2 register under the same conditions as HVC instructions 393 * and when the processor supports ECV. 394 */ 395 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 396 || ((GET_RW(ep->spsr) != MODE_RW_64) 397 && (GET_M32(ep->spsr) == MODE32_hyp))) { 398 scr_el3 |= SCR_HCE_BIT; 399 400 if (is_feat_fgt_supported()) { 401 scr_el3 |= SCR_FGTEN_BIT; 402 } 403 404 if (is_feat_ecv_supported()) { 405 scr_el3 |= SCR_ECVEN_BIT; 406 } 407 } 408 409 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 410 if (is_feat_twed_supported()) { 411 /* Set delay in SCR_EL3 */ 412 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 413 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 414 << SCR_TWEDEL_SHIFT); 415 416 /* Enable WFE delay */ 417 scr_el3 |= SCR_TWEDEn_BIT; 418 } 419 420 /* 421 * Populate EL3 state so that we've the right context 422 * before doing ERET 423 */ 424 state = get_el3state_ctx(ctx); 425 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 426 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 427 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 428 429 /* 430 * Store the X0-X7 value from the entrypoint into the context 431 * Use memcpy as we are in control of the layout of the structures 432 */ 433 gp_regs = get_gpregs_ctx(ctx); 434 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 435 } 436 437 /******************************************************************************* 438 * Context management library initialization routine. This library is used by 439 * runtime services to share pointers to 'cpu_context' structures for secure 440 * non-secure and realm states. Management of the structures and their associated 441 * memory is not done by the context management library e.g. the PSCI service 442 * manages the cpu context used for entry from and exit to the non-secure state. 443 * The Secure payload dispatcher service manages the context(s) corresponding to 444 * the secure state. It also uses this library to get access to the non-secure 445 * state cpu context pointers. 446 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 447 * which will be used for programming an entry into a lower EL. The same context 448 * will be used to save state upon exception entry from that EL. 449 ******************************************************************************/ 450 void __init cm_init(void) 451 { 452 /* 453 * The context management library has only global data to intialize, but 454 * that will be done when the BSS is zeroed out. 455 */ 456 } 457 458 /******************************************************************************* 459 * This is the high-level function used to initialize the cpu_context 'ctx' for 460 * first use. It performs initializations that are common to all security states 461 * and initializations specific to the security state specified in 'ep' 462 ******************************************************************************/ 463 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 464 { 465 unsigned int security_state; 466 467 assert(ctx != NULL); 468 469 /* 470 * Perform initializations that are common 471 * to all security states 472 */ 473 setup_context_common(ctx, ep); 474 475 security_state = GET_SECURITY_STATE(ep->h.attr); 476 477 /* Perform security state specific initializations */ 478 switch (security_state) { 479 case SECURE: 480 setup_secure_context(ctx, ep); 481 break; 482 #if ENABLE_RME 483 case REALM: 484 setup_realm_context(ctx, ep); 485 break; 486 #endif 487 case NON_SECURE: 488 setup_ns_context(ctx, ep); 489 break; 490 default: 491 ERROR("Invalid security state\n"); 492 panic(); 493 break; 494 } 495 } 496 497 /******************************************************************************* 498 * Enable architecture extensions on first entry to Non-secure world. 499 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 500 * it is zero. 501 ******************************************************************************/ 502 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 503 { 504 #if IMAGE_BL31 505 if (is_feat_spe_supported()) { 506 spe_enable(el2_unused); 507 } 508 509 if (is_feat_amu_supported()) { 510 amu_enable(el2_unused, ctx); 511 } 512 513 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 514 if (is_feat_sme_supported()) { 515 sme_enable(ctx); 516 } else if (is_feat_sve_supported()) { 517 /* Enable SVE and FPU/SIMD for non-secure world. */ 518 sve_enable(ctx); 519 } 520 521 if (is_feat_mpam_supported()) { 522 mpam_enable(el2_unused); 523 } 524 525 if (is_feat_trbe_supported()) { 526 trbe_enable(); 527 } 528 529 if (is_feat_brbe_supported()) { 530 brbe_enable(); 531 } 532 533 if (is_feat_sys_reg_trace_supported()) { 534 sys_reg_trace_enable(ctx); 535 } 536 537 if (is_feat_trf_supported()) { 538 trf_enable(); 539 } 540 #endif 541 } 542 543 /******************************************************************************* 544 * Enable architecture extensions on first entry to Secure world. 545 ******************************************************************************/ 546 static void manage_extensions_secure(cpu_context_t *ctx) 547 { 548 #if IMAGE_BL31 549 550 if (is_feat_sme_supported()) { 551 if (ENABLE_SME_FOR_SWD) { 552 /* 553 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 554 * must ensure SME, SVE, and FPU/SIMD context properly managed. 555 */ 556 sme_enable(ctx); 557 } else { 558 /* 559 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 560 * world can safely use the associated registers. 561 */ 562 sme_disable(ctx); 563 } 564 } else if (is_feat_sve_supported()) { 565 if (ENABLE_SVE_FOR_SWD) { 566 /* 567 * Enable SVE and FPU in secure context, secure manager must 568 * ensure that the SVE and FPU register contexts are properly 569 * managed. 570 */ 571 sve_enable(ctx); 572 } else { 573 /* 574 * Disable SVE and FPU in secure context so non-secure world 575 * can safely use them. 576 */ 577 sve_disable(ctx); 578 } 579 } 580 581 #endif /* IMAGE_BL31 */ 582 } 583 584 /******************************************************************************* 585 * The following function initializes the cpu_context for a CPU specified by 586 * its `cpu_idx` for first use, and sets the initial entrypoint state as 587 * specified by the entry_point_info structure. 588 ******************************************************************************/ 589 void cm_init_context_by_index(unsigned int cpu_idx, 590 const entry_point_info_t *ep) 591 { 592 cpu_context_t *ctx; 593 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 594 cm_setup_context(ctx, ep); 595 } 596 597 /******************************************************************************* 598 * The following function initializes the cpu_context for the current CPU 599 * for first use, and sets the initial entrypoint state as specified by the 600 * entry_point_info structure. 601 ******************************************************************************/ 602 void cm_init_my_context(const entry_point_info_t *ep) 603 { 604 cpu_context_t *ctx; 605 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 606 cm_setup_context(ctx, ep); 607 } 608 609 /******************************************************************************* 610 * Prepare the CPU system registers for first entry into realm, secure, or 611 * normal world. 612 * 613 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 614 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 615 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 616 * For all entries, the EL1 registers are initialized from the cpu_context 617 ******************************************************************************/ 618 void cm_prepare_el3_exit(uint32_t security_state) 619 { 620 u_register_t sctlr_elx, scr_el3, mdcr_el2; 621 cpu_context_t *ctx = cm_get_context(security_state); 622 bool el2_unused = false; 623 uint64_t hcr_el2 = 0U; 624 625 assert(ctx != NULL); 626 627 if (security_state == NON_SECURE) { 628 uint64_t el2_implemented = el_implemented(2); 629 630 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 631 CTX_SCR_EL3); 632 633 if (((scr_el3 & SCR_HCE_BIT) != 0U) 634 || (el2_implemented != EL_IMPL_NONE)) { 635 /* 636 * If context is not being used for EL2, initialize 637 * HCRX_EL2 with its init value here. 638 */ 639 if (is_feat_hcx_supported()) { 640 write_hcrx_el2(HCRX_EL2_INIT_VAL); 641 } 642 } 643 644 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 645 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 646 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 647 CTX_SCTLR_EL1); 648 sctlr_elx &= SCTLR_EE_BIT; 649 sctlr_elx |= SCTLR_EL2_RES1; 650 #if ERRATA_A75_764081 651 /* 652 * If workaround of errata 764081 for Cortex-A75 is used 653 * then set SCTLR_EL2.IESB to enable Implicit Error 654 * Synchronization Barrier. 655 */ 656 sctlr_elx |= SCTLR_IESB_BIT; 657 #endif 658 write_sctlr_el2(sctlr_elx); 659 } else if (el2_implemented != EL_IMPL_NONE) { 660 el2_unused = true; 661 662 /* 663 * EL2 present but unused, need to disable safely. 664 * SCTLR_EL2 can be ignored in this case. 665 * 666 * Set EL2 register width appropriately: Set HCR_EL2 667 * field to match SCR_EL3.RW. 668 */ 669 if ((scr_el3 & SCR_RW_BIT) != 0U) 670 hcr_el2 |= HCR_RW_BIT; 671 672 /* 673 * For Armv8.3 pointer authentication feature, disable 674 * traps to EL2 when accessing key registers or using 675 * pointer authentication instructions from lower ELs. 676 */ 677 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 678 679 write_hcr_el2(hcr_el2); 680 681 /* 682 * Initialise CPTR_EL2 setting all fields rather than 683 * relying on the hw. All fields have architecturally 684 * UNKNOWN reset values. 685 * 686 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 687 * accesses to the CPACR_EL1 or CPACR from both 688 * Execution states do not trap to EL2. 689 * 690 * CPTR_EL2.TTA: Set to zero so that Non-secure System 691 * register accesses to the trace registers from both 692 * Execution states do not trap to EL2. 693 * If PE trace unit System registers are not implemented 694 * then this bit is reserved, and must be set to zero. 695 * 696 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 697 * to SIMD and floating-point functionality from both 698 * Execution states do not trap to EL2. 699 */ 700 write_cptr_el2(CPTR_EL2_RESET_VAL & 701 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 702 | CPTR_EL2_TFP_BIT)); 703 704 /* 705 * Initialise CNTHCTL_EL2. All fields are 706 * architecturally UNKNOWN on reset and are set to zero 707 * except for field(s) listed below. 708 * 709 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 710 * Hyp mode of Non-secure EL0 and EL1 accesses to the 711 * physical timer registers. 712 * 713 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 714 * Hyp mode of Non-secure EL0 and EL1 accesses to the 715 * physical counter registers. 716 */ 717 write_cnthctl_el2(CNTHCTL_RESET_VAL | 718 EL1PCEN_BIT | EL1PCTEN_BIT); 719 720 /* 721 * Initialise CNTVOFF_EL2 to zero as it resets to an 722 * architecturally UNKNOWN value. 723 */ 724 write_cntvoff_el2(0); 725 726 /* 727 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 728 * MPIDR_EL1 respectively. 729 */ 730 write_vpidr_el2(read_midr_el1()); 731 write_vmpidr_el2(read_mpidr_el1()); 732 733 /* 734 * Initialise VTTBR_EL2. All fields are architecturally 735 * UNKNOWN on reset. 736 * 737 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 738 * 2 address translation is disabled, cache maintenance 739 * operations depend on the VMID. 740 * 741 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 742 * translation is disabled. 743 */ 744 write_vttbr_el2(VTTBR_RESET_VAL & 745 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 746 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 747 748 /* 749 * Initialise MDCR_EL2, setting all fields rather than 750 * relying on hw. Some fields are architecturally 751 * UNKNOWN on reset. 752 * 753 * MDCR_EL2.HLP: Set to one so that event counter 754 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 755 * occurs on the increment that changes 756 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 757 * implemented. This bit is RES0 in versions of the 758 * architecture earlier than ARMv8.5, setting it to 1 759 * doesn't have any effect on them. 760 * 761 * MDCR_EL2.TTRF: Set to zero so that access to Trace 762 * Filter Control register TRFCR_EL1 at EL1 is not 763 * trapped to EL2. This bit is RES0 in versions of 764 * the architecture earlier than ARMv8.4. 765 * 766 * MDCR_EL2.HPMD: Set to one so that event counting is 767 * prohibited at EL2. This bit is RES0 in versions of 768 * the architecture earlier than ARMv8.1, setting it 769 * to 1 doesn't have any effect on them. 770 * 771 * MDCR_EL2.TPMS: Set to zero so that accesses to 772 * Statistical Profiling control registers from EL1 773 * do not trap to EL2. This bit is RES0 when SPE is 774 * not implemented. 775 * 776 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 777 * EL1 System register accesses to the Debug ROM 778 * registers are not trapped to EL2. 779 * 780 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 781 * System register accesses to the powerdown debug 782 * registers are not trapped to EL2. 783 * 784 * MDCR_EL2.TDA: Set to zero so that System register 785 * accesses to the debug registers do not trap to EL2. 786 * 787 * MDCR_EL2.TDE: Set to zero so that debug exceptions 788 * are not routed to EL2. 789 * 790 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 791 * Monitors. 792 * 793 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 794 * EL1 accesses to all Performance Monitors registers 795 * are not trapped to EL2. 796 * 797 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 798 * and EL1 accesses to the PMCR_EL0 or PMCR are not 799 * trapped to EL2. 800 * 801 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 802 * architecturally-defined reset value. 803 * 804 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 805 * owning exception level is NS-EL1 and, tracing is 806 * prohibited at NS-EL2. These bits are RES0 when 807 * FEAT_TRBE is not implemented. 808 */ 809 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 810 MDCR_EL2_HPMD) | 811 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 812 >> PMCR_EL0_N_SHIFT)) & 813 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 814 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 815 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 816 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 817 MDCR_EL2_TPMCR_BIT | 818 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 819 820 write_mdcr_el2(mdcr_el2); 821 822 /* 823 * Initialise HSTR_EL2. All fields are architecturally 824 * UNKNOWN on reset. 825 * 826 * HSTR_EL2.T<n>: Set all these fields to zero so that 827 * Non-secure EL0 or EL1 accesses to System registers 828 * do not trap to EL2. 829 */ 830 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 831 /* 832 * Initialise CNTHP_CTL_EL2. All fields are 833 * architecturally UNKNOWN on reset. 834 * 835 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 836 * physical timer and prevent timer interrupts. 837 */ 838 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 839 ~(CNTHP_CTL_ENABLE_BIT)); 840 } 841 manage_extensions_nonsecure(el2_unused, ctx); 842 } 843 844 cm_el1_sysregs_context_restore(security_state); 845 cm_set_next_eret_context(security_state); 846 } 847 848 #if CTX_INCLUDE_EL2_REGS 849 850 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 851 { 852 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 853 if (is_feat_amu_supported()) { 854 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 855 } 856 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 857 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 858 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 859 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 860 } 861 862 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 863 { 864 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 865 if (is_feat_amu_supported()) { 866 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 867 } 868 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 869 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 870 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 871 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 872 } 873 874 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 875 { 876 u_register_t mpam_idr = read_mpamidr_el1(); 877 878 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 879 880 /* 881 * The context registers that we intend to save would be part of the 882 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 883 */ 884 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 885 return; 886 } 887 888 /* 889 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 890 * MPAMIDR_HAS_HCR_BIT == 1. 891 */ 892 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 893 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 894 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 895 896 /* 897 * The number of MPAMVPM registers is implementation defined, their 898 * number is stored in the MPAMIDR_EL1 register. 899 */ 900 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 901 case 7: 902 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 903 __fallthrough; 904 case 6: 905 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 906 __fallthrough; 907 case 5: 908 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 909 __fallthrough; 910 case 4: 911 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 912 __fallthrough; 913 case 3: 914 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 915 __fallthrough; 916 case 2: 917 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 918 __fallthrough; 919 case 1: 920 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 921 break; 922 } 923 } 924 925 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 926 { 927 u_register_t mpam_idr = read_mpamidr_el1(); 928 929 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 930 931 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 932 return; 933 } 934 935 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 936 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 937 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 938 939 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 940 case 7: 941 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 942 __fallthrough; 943 case 6: 944 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 945 __fallthrough; 946 case 5: 947 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 948 __fallthrough; 949 case 4: 950 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 951 __fallthrough; 952 case 3: 953 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 954 __fallthrough; 955 case 2: 956 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 957 __fallthrough; 958 case 1: 959 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 960 break; 961 } 962 } 963 964 /******************************************************************************* 965 * Save EL2 sysreg context 966 ******************************************************************************/ 967 void cm_el2_sysregs_context_save(uint32_t security_state) 968 { 969 u_register_t scr_el3 = read_scr(); 970 971 /* 972 * Always save the non-secure and realm EL2 context, only save the 973 * S-EL2 context if S-EL2 is enabled. 974 */ 975 if ((security_state != SECURE) || 976 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 977 cpu_context_t *ctx; 978 el2_sysregs_t *el2_sysregs_ctx; 979 980 ctx = cm_get_context(security_state); 981 assert(ctx != NULL); 982 983 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 984 985 el2_sysregs_context_save_common(el2_sysregs_ctx); 986 #if CTX_INCLUDE_MTE_REGS 987 el2_sysregs_context_save_mte(el2_sysregs_ctx); 988 #endif 989 if (is_feat_mpam_supported()) { 990 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 991 } 992 993 if (is_feat_fgt_supported()) { 994 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 995 } 996 997 if (is_feat_ecv_v2_supported()) { 998 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 999 read_cntpoff_el2()); 1000 } 1001 1002 if (is_feat_vhe_supported()) { 1003 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 1004 read_contextidr_el2()); 1005 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 1006 read_ttbr1_el2()); 1007 } 1008 #if RAS_EXTENSION 1009 el2_sysregs_context_save_ras(el2_sysregs_ctx); 1010 #endif 1011 1012 if (is_feat_nv2_supported()) { 1013 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1014 read_vncr_el2()); 1015 } 1016 1017 if (is_feat_trf_supported()) { 1018 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1019 } 1020 1021 if (is_feat_csv2_2_supported()) { 1022 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1023 read_scxtnum_el2()); 1024 } 1025 1026 if (is_feat_hcx_supported()) { 1027 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1028 } 1029 if (is_feat_tcr2_supported()) { 1030 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1031 } 1032 if (is_feat_sxpie_supported()) { 1033 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1034 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1035 } 1036 if (is_feat_s2pie_supported()) { 1037 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1038 } 1039 if (is_feat_sxpoe_supported()) { 1040 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1041 } 1042 } 1043 } 1044 1045 /******************************************************************************* 1046 * Restore EL2 sysreg context 1047 ******************************************************************************/ 1048 void cm_el2_sysregs_context_restore(uint32_t security_state) 1049 { 1050 u_register_t scr_el3 = read_scr(); 1051 1052 /* 1053 * Always restore the non-secure and realm EL2 context, only restore the 1054 * S-EL2 context if S-EL2 is enabled. 1055 */ 1056 if ((security_state != SECURE) || 1057 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1058 cpu_context_t *ctx; 1059 el2_sysregs_t *el2_sysregs_ctx; 1060 1061 ctx = cm_get_context(security_state); 1062 assert(ctx != NULL); 1063 1064 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1065 1066 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1067 #if CTX_INCLUDE_MTE_REGS 1068 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 1069 #endif 1070 if (is_feat_mpam_supported()) { 1071 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1072 } 1073 1074 if (is_feat_fgt_supported()) { 1075 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1076 } 1077 1078 if (is_feat_ecv_v2_supported()) { 1079 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1080 CTX_CNTPOFF_EL2)); 1081 } 1082 1083 if (is_feat_vhe_supported()) { 1084 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1085 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1086 } 1087 #if RAS_EXTENSION 1088 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 1089 #endif 1090 1091 if (is_feat_nv2_supported()) { 1092 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1093 } 1094 if (is_feat_trf_supported()) { 1095 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1096 } 1097 1098 if (is_feat_csv2_2_supported()) { 1099 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1100 CTX_SCXTNUM_EL2)); 1101 } 1102 1103 if (is_feat_hcx_supported()) { 1104 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1105 } 1106 if (is_feat_tcr2_supported()) { 1107 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1108 } 1109 if (is_feat_sxpie_supported()) { 1110 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1111 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1112 } 1113 if (is_feat_s2pie_supported()) { 1114 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1115 } 1116 if (is_feat_sxpoe_supported()) { 1117 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1118 } 1119 } 1120 } 1121 #endif /* CTX_INCLUDE_EL2_REGS */ 1122 1123 /******************************************************************************* 1124 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1125 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1126 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1127 * cm_prepare_el3_exit function. 1128 ******************************************************************************/ 1129 void cm_prepare_el3_exit_ns(void) 1130 { 1131 #if CTX_INCLUDE_EL2_REGS 1132 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1133 assert(ctx != NULL); 1134 1135 /* Assert that EL2 is used. */ 1136 #if ENABLE_ASSERTIONS 1137 el3_state_t *state = get_el3state_ctx(ctx); 1138 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1139 #endif 1140 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1141 (el_implemented(2U) != EL_IMPL_NONE)); 1142 1143 /* 1144 * Currently some extensions are configured using 1145 * direct register updates. Therefore, do this here 1146 * instead of when setting up context. 1147 */ 1148 manage_extensions_nonsecure(0, ctx); 1149 1150 /* 1151 * Set the NS bit to be able to access the ICC_SRE_EL2 1152 * register when restoring context. 1153 */ 1154 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1155 1156 /* 1157 * Ensure the NS bit change is committed before the EL2/EL1 1158 * state restoration. 1159 */ 1160 isb(); 1161 1162 /* Restore EL2 and EL1 sysreg contexts */ 1163 cm_el2_sysregs_context_restore(NON_SECURE); 1164 cm_el1_sysregs_context_restore(NON_SECURE); 1165 cm_set_next_eret_context(NON_SECURE); 1166 #else 1167 cm_prepare_el3_exit(NON_SECURE); 1168 #endif /* CTX_INCLUDE_EL2_REGS */ 1169 } 1170 1171 /******************************************************************************* 1172 * The next four functions are used by runtime services to save and restore 1173 * EL1 context on the 'cpu_context' structure for the specified security 1174 * state. 1175 ******************************************************************************/ 1176 void cm_el1_sysregs_context_save(uint32_t security_state) 1177 { 1178 cpu_context_t *ctx; 1179 1180 ctx = cm_get_context(security_state); 1181 assert(ctx != NULL); 1182 1183 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1184 1185 #if IMAGE_BL31 1186 if (security_state == SECURE) 1187 PUBLISH_EVENT(cm_exited_secure_world); 1188 else 1189 PUBLISH_EVENT(cm_exited_normal_world); 1190 #endif 1191 } 1192 1193 void cm_el1_sysregs_context_restore(uint32_t security_state) 1194 { 1195 cpu_context_t *ctx; 1196 1197 ctx = cm_get_context(security_state); 1198 assert(ctx != NULL); 1199 1200 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1201 1202 #if IMAGE_BL31 1203 if (security_state == SECURE) 1204 PUBLISH_EVENT(cm_entering_secure_world); 1205 else 1206 PUBLISH_EVENT(cm_entering_normal_world); 1207 #endif 1208 } 1209 1210 /******************************************************************************* 1211 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1212 * given security state with the given entrypoint 1213 ******************************************************************************/ 1214 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1215 { 1216 cpu_context_t *ctx; 1217 el3_state_t *state; 1218 1219 ctx = cm_get_context(security_state); 1220 assert(ctx != NULL); 1221 1222 /* Populate EL3 state so that ERET jumps to the correct entry */ 1223 state = get_el3state_ctx(ctx); 1224 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1225 } 1226 1227 /******************************************************************************* 1228 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1229 * pertaining to the given security state 1230 ******************************************************************************/ 1231 void cm_set_elr_spsr_el3(uint32_t security_state, 1232 uintptr_t entrypoint, uint32_t spsr) 1233 { 1234 cpu_context_t *ctx; 1235 el3_state_t *state; 1236 1237 ctx = cm_get_context(security_state); 1238 assert(ctx != NULL); 1239 1240 /* Populate EL3 state so that ERET jumps to the correct entry */ 1241 state = get_el3state_ctx(ctx); 1242 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1243 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1244 } 1245 1246 /******************************************************************************* 1247 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1248 * pertaining to the given security state using the value and bit position 1249 * specified in the parameters. It preserves all other bits. 1250 ******************************************************************************/ 1251 void cm_write_scr_el3_bit(uint32_t security_state, 1252 uint32_t bit_pos, 1253 uint32_t value) 1254 { 1255 cpu_context_t *ctx; 1256 el3_state_t *state; 1257 u_register_t scr_el3; 1258 1259 ctx = cm_get_context(security_state); 1260 assert(ctx != NULL); 1261 1262 /* Ensure that the bit position is a valid one */ 1263 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1264 1265 /* Ensure that the 'value' is only a bit wide */ 1266 assert(value <= 1U); 1267 1268 /* 1269 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1270 * and set it to its new value. 1271 */ 1272 state = get_el3state_ctx(ctx); 1273 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1274 scr_el3 &= ~(1UL << bit_pos); 1275 scr_el3 |= (u_register_t)value << bit_pos; 1276 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1277 } 1278 1279 /******************************************************************************* 1280 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1281 * given security state. 1282 ******************************************************************************/ 1283 u_register_t cm_get_scr_el3(uint32_t security_state) 1284 { 1285 cpu_context_t *ctx; 1286 el3_state_t *state; 1287 1288 ctx = cm_get_context(security_state); 1289 assert(ctx != NULL); 1290 1291 /* Populate EL3 state so that ERET jumps to the correct entry */ 1292 state = get_el3state_ctx(ctx); 1293 return read_ctx_reg(state, CTX_SCR_EL3); 1294 } 1295 1296 /******************************************************************************* 1297 * This function is used to program the context that's used for exception 1298 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1299 * the required security state 1300 ******************************************************************************/ 1301 void cm_set_next_eret_context(uint32_t security_state) 1302 { 1303 cpu_context_t *ctx; 1304 1305 ctx = cm_get_context(security_state); 1306 assert(ctx != NULL); 1307 1308 cm_set_next_context(ctx); 1309 } 1310